RssiAxiLiteRegItf Entity Reference

Inheritance diagram for RssiAxiLiteRegItf:

Collaboration diagram for RssiAxiLiteRegItf:

Entities
RssiAxiLiteRegItf.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
RssiPkg	Package <RssiPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SEGMENT_ADDR_SIZE_G	positive := 7
TIMEOUT_UNIT_G	real := 1 . 0E - 6
INIT_SEQ_N_G	natural := 16#80#
CONN_ID_G	positive := 16#12345678#
VERSION_G	positive := 1
HEADER_CHKSUM_EN_G	boolean := true
MAX_NUM_OUTS_SEG_G	positive := 8
MAX_SEG_SIZE_G	positive := 1024
RETRANS_TOUT_G	positive := 50
ACK_TOUT_G	positive := 25
NULL_TOUT_G	positive := 200
MAX_RETRANS_CNT_G	positive := 2
MAX_CUM_ACK_CNT_G	positive := 3
MAX_OUT_OF_SEQUENCE_G	natural := 3

Ports
axiClk_i	in	sl
axiRst_i	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
devClk_i	in	sl
devRst_i	in	sl
openRq_o	out	sl
closeRq_o	out	sl
mode_o	out	sl
injectFault_o	out	sl
initSeqN_o	out	slv ( 7 downto 0 )
appRssiParam_o	out	RssiParamType
negRssiParam_i	in	RssiParamType
txLastAckN_i	in	slv ( 7 downto 0 )
rxSeqN_i	in	slv ( 7 downto 0 )
rxAckN_i	in	slv ( 7 downto 0 )
rxLastSeqN_i	in	slv ( 7 downto 0 )
txTspState_i	in	slv ( 7 downto 0 )
txAppState_i	in	slv ( 3 downto 0 )
txAckState_i	in	slv ( 3 downto 0 )
rxTspState_i	in	slv ( 3 downto 0 )
rxAppState_i	in	slv ( 3 downto 0 )
connState_i	in	slv ( 3 downto 0 )
frameRate_i	in	Slv32Array ( 1 downto 0 )
bandwidth_i	in	Slv64Array ( 1 downto 0 )
status_i	in	slv ( 8 downto 0 )
dropCnt_i	in	slv ( 31 downto 0 )
validCnt_i	in	slv ( 31 downto 0 )
resendCnt_i	in	slv ( 31 downto 0 )
reconCnt_i	in	slv ( 31 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiAxiLiteRegItf.vhd
• protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd