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RssiAxiLiteRegItf.rtl Architecture Reference
Architecture >> RssiAxiLiteRegItf::rtl

Processes

comb  ( axiRst_i , axilReadMaster , axilWriteMaster , bandwidth_i , connState_i , frameRate_i , negRssiParam , r , rxAckN_i , rxAppState_i , rxLastSeqN_i , rxSeqN_i , rxTspState_i , s_RdAddr , s_WrAddr , s_dropCnt , s_reconCnt , s_resendCnt , s_status , s_validCnt , txAckState_i , txAppState_i , txLastAckN_i , txTspState_i )
seq  ( axiClk_i )
comb  ( axiRst_i , axilReadMaster , axilWriteMaster , bandwidth_i , connState_i , frameRate_i , negRssiParam , r , rxAckN_i , rxAppState_i , rxLastSeqN_i , rxSeqN_i , rxTspState_i , s_RdAddr , s_WrAddr , s_dropCnt , s_reconCnt , s_resendCnt , s_status , s_validCnt , txAckState_i , txAppState_i , txLastAckN_i , txTspState_i )
seq  ( axiClk_i )

Constants

REG_INIT_C  RegType := ( control = > " 01000 " , initSeqN = > toSlv ( INIT_SEQ_N_G , 8 ) , appRssiParam = > ( version = > toSlv ( VERSION_G , 4 ) , chksumEn = > " 1 " , timeoutUnit = > toSlv ( integer ( 0 . 0 - ( ieee.math_real.log ( TIMEOUT_UNIT_G ) / ieee.math_real.log ( 10 . 0 ) ) ) , 8 ) , maxOutsSeg = > toSlv ( MAX_NUM_OUTS_SEG_G , 8 ) , maxSegSize = > toSlv ( MAX_SEG_SIZE_G , 16 ) , retransTout = > toSlv ( RETRANS_TOUT_G , 16 ) , cumulAckTout = > toSlv ( ACK_TOUT_G , 16 ) , nullSegTout = > toSlv ( NULL_TOUT_G , 16 ) , maxRetrans = > toSlv ( MAX_RETRANS_CNT_G , 8 ) , maxCumAck = > toSlv ( MAX_CUM_ACK_CNT_G , 8 ) , maxOutofseq = > toSlv ( MAX_OUT_OF_SEQUENCE_G , 8 ) , connectionId = > toSlv ( CONN_ID_G , 32 ) ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals

r  RegType := REG_INIT_C
rin  RegType
s_RdAddr  natural := 0
s_WrAddr  natural := 0
s_status  slv ( status_i )
s_dropCnt  slv ( 31 downto 0 )
s_validCnt  slv ( 31 downto 0 )
s_reconCnt  slv ( 31 downto 0 )
s_resendCnt  slv ( 31 downto 0 )
dummyBit  sl
negRssiParam  RssiParamType

Records

RegType 

Instantiations

u_status  SynchronizerVector <Entity SynchronizerVector>
u_validcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_dropcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_resendcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_reconcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_syncvecout  SynchronizerVector <Entity SynchronizerVector>
u_initseqn  SynchronizerVector <Entity SynchronizerVector>
u_rssiparamsync_in  RssiParamSync <Entity RssiParamSync>
u_rssiparamsync_out  RssiParamSync <Entity RssiParamSync>
u_status  SynchronizerVector <Entity SynchronizerVector>
u_validcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_dropcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_resendcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_reconcnt  SynchronizerFifo <Entity SynchronizerFifo>
u_syncvecout  SynchronizerVector <Entity SynchronizerVector>
u_initseqn  SynchronizerVector <Entity SynchronizerVector>
u_rssiparamsync_in  RssiParamSync <Entity RssiParamSync>
u_rssiparamsync_out  RssiParamSync <Entity RssiParamSync>

The documentation for this design unit was generated from the following files: