RssiRxFsm Entity Reference

Inheritance diagram for RssiRxFsm:

Entities
RssiRxFsm.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
RssiPkg	Package <RssiPkg>
SsiPkg	Package <SsiPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
WINDOW_ADDR_SIZE_G	positive := 7
HEADER_CHKSUM_EN_G	boolean := true
SEGMENT_ADDR_SIZE_G	positive := 3

Ports
clk_i	in	sl
rst_i	in	sl
connActive_i	in	sl
rxWindowSize_i	in	integer range 1 to 2 ** ( WINDOW_ADDR_SIZE_G )
rxBufferSize_i	in	integer range 1 to 2 ** ( SEGMENT_ADDR_SIZE_G )
txWindowSize_i	in	integer range 1 to 2 ** ( WINDOW_ADDR_SIZE_G )
lastAckN_i	in	slv ( 7 downto 0 )
rxSeqN_o	out	slv ( 7 downto 0 )
rxAckN_o	out	slv ( 7 downto 0 )
rxLastSeqN_o	out	slv ( 7 downto 0 )
rxValidSeg_o	out	sl
rxDropSeg_o	out	sl
rxFlags_o	out	flagsType
rxParam_o	out	RssiParamType
rxTspState_o	out	slv ( 3 downto 0 )
rxAppState_o	out	slv ( 3 downto 0 )
chksumValid_i	in	sl
chksumOk_i	in	sl
chksumEnable_o	out	sl
chksumStrobe_o	out	sl
chksumLength_o	out	positive
wrBuffWe_o	out	sl
wrBuffAddr_o	out	slv ( ( SEGMENT_ADDR_SIZE_G+ WINDOW_ADDR_SIZE_G ) - 1 downto 0 )
wrBuffData_o	out	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
rdBuffAddr_o	out	slv ( ( SEGMENT_ADDR_SIZE_G+ WINDOW_ADDR_SIZE_G ) - 1 downto 0 )
rdBuffData_i	in	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
tspSsiMaster_i	in	SsiMasterType
tspSsiSlave_o	out	SsiSlaveType
appSsiMaster_o	out	SsiMasterType
appSsiSlave_i	in	SsiSlaveType

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiRxFsm.vhd
• protocols/rssi/v1/rtl/RssiRxFsm.vhd