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RssiChksum Entity Reference
Inheritance diagram for RssiChksum:Entities | |
| RssiChksum.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
Generics | |
| TPD_G | time := 1 ns |
| DATA_WIDTH_G | positive := 64 |
| CSUM_WIDTH_G | positive := 16 |
Ports | ||
| clk_i | in | sl |
| rst_i | in | sl |
| enable_i | in | sl |
| strobe_i | in | sl |
| length_i | in | positive |
| init_i | in | slv ( CSUM_WIDTH_G- 1 downto 0 ) |
| data_i | in | slv ( DATA_WIDTH_G- 1 downto 0 ) |
| chksum_o | out | slv ( CSUM_WIDTH_G- 1 downto 0 ) |
| valid_o | out | sl |
| check_o | out | sl |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/RssiChksum.vhd
- protocols/rssi/v1/rtl/RssiChksum.vhd
