RssiChksum.rtl Architecture Reference

Architecture >> RssiChksum::rtl

Processes
comb	( enable_i , init_i , length_i , r , rst_i , s_dataWordSum , strobe_i )
seq	( clk_i )
comb	( enable_i , init_i , length_i , r , rst_i , s_dataWordSum , strobe_i )
seq	( clk_i )

Constants
RATIO_C	positive := DATA_WIDTH_G/ CSUM_WIDTH_G
REG_INIT_C	RegType := ( sum = > ( others = > ' 0 ' ) , chksum = > ( others = > ' 0 ' ) , lenCnt = > 0 , valid = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_dataWordSum	slv ( CSUM_WIDTH_G+ 1 downto 0 )

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiChksum.vhd
• protocols/rssi/v1/rtl/RssiChksum.vhd