SURF
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RssiTxFsm Entity Reference
+ Inheritance diagram for RssiTxFsm:

Entities

RssiTxFsm.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
RssiPkg  Package <RssiPkg>
SsiPkg  Package <SsiPkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

TPD_G  time := 1 ns
WINDOW_ADDR_SIZE_G  positive := 3
SEGMENT_ADDR_SIZE_G  positive := 7
SYN_HEADER_SIZE_G  natural := 24
ACK_HEADER_SIZE_G  natural := 8
EACK_HEADER_SIZE_G  natural := 8
RST_HEADER_SIZE_G  natural := 8
NULL_HEADER_SIZE_G  natural := 8
DATA_HEADER_SIZE_G  natural := 8
HEADER_CHKSUM_EN_G  boolean := true

Ports

clk_i   in   sl
rst_i   in   sl
connActive_i   in   sl
closed_i   in   sl
injectFault_i   in   sl
sndSyn_i   in   sl
sndAck_i   in   sl
sndRst_i   in   sl
sndResend_i   in   sl
sndNull_i   in   sl
windowSize_i   in   integer range 1 to 2 ** ( WINDOW_ADDR_SIZE_G )
bufferSize_i   in   integer range 1 to 2 ** ( SEGMENT_ADDR_SIZE_G )
wrBuffWe_o   out   sl
wrBuffAddr_o   out   slv ( ( SEGMENT_ADDR_SIZE_G+ WINDOW_ADDR_SIZE_G ) - 1 downto 0 )
wrBuffData_o   out   slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
rdBuffAddr_o   out   slv ( ( SEGMENT_ADDR_SIZE_G+ WINDOW_ADDR_SIZE_G ) - 1 downto 0 )
rdBuffData_i   in   slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
rdHeaderAddr_o   out   slv ( 7 downto 0 )
rdHeaderData_i   in   slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
headerRdy_i   in   sl
headerLength_i   in   positive
chksumValid_i   in   sl
chksumEnable_o   out   sl
chksumStrobe_o   out   sl
chksum_i   in   slv ( 15 downto 0 )
initSeqN_i   in   slv ( 7 downto 0 )
txSeqN_o   out   slv ( 7 downto 0 )
synHeadSt_o   out   sl
ackHeadSt_o   out   sl
dataHeadSt_o   out   sl
dataSt_o   out   sl
rstHeadSt_o   out   sl
nullHeadSt_o   out   sl
txTspState_o   out   slv ( 7 downto 0 )
txAppState_o   out   slv ( 3 downto 0 )
txAckState_o   out   slv ( 3 downto 0 )
lastAckN_o   out   slv ( 7 downto 0 )
ack_i   in   sl
ackN_i   in   slv ( 7 downto 0 )
appSsiMaster_i   in   SsiMasterType
appSsiSlave_o   out   SsiSlaveType
tspSsiSlave_i   in   SsiSlaveType
tspSsiMaster_o   out   SsiMasterType
lenErr_o   out   sl
ackErr_o   out   sl
bufferEmpty_o   out   sl

The documentation for this design unit was generated from the following files: