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RssiTxFsm.rtl Architecture Reference
Architecture >> RssiTxFsm::rtl

Processes

comb  ( ackN_i , ack_i , appSsiMaster_i , bufferSize_i , chksumValid_i , closed_i , connActive_i , headerLength_i , headerRdy_i , initSeqN_i , injectFault_i , r , rdBuffData_i , rdHeaderData_i , rst_i , s_headerAndChksum , sndAck_i , sndNull_i , sndResend_i , sndRst_i , sndSyn_i , tspSsiSlave_i , windowSize_i )
seq  ( clk_i )
comb  ( ackN_i , ack_i , appSsiMaster_i , bufferSize_i , chksumValid_i , closed_i , connActive_i , headerLength_i , headerRdy_i , initSeqN_i , injectFault_i , r , rdBuffData_i , rdHeaderData_i , rst_i , s_headerAndChksum , sndAck_i , sndNull_i , sndResend_i , sndRst_i , sndSyn_i , tspSsiSlave_i , windowSize_i )
seq  ( clk_i )

Constants

SSI_MASTER_INIT_C  SsiMasterType := axis2SsiMaster ( RSSI_AXIS_CONFIG_C , AXI_STREAM_MASTER_INIT_C )
SSI_SLAVE_NOTRDY_C  SsiSlaveType := axis2SsiSlave ( RSSI_AXIS_CONFIG_C , AXI_STREAM_SLAVE_INIT_C , AXI_STREAM_CTRL_INIT_C )
SSI_SLAVE_RDY_C  SsiSlaveType := axis2SsiSlave ( RSSI_AXIS_CONFIG_C , AXI_STREAM_SLAVE_FORCE_C , AXI_STREAM_CTRL_INIT_C )
REG_INIT_C  RegType := ( firstUnackAddr = > ( others = > ' 0 ' ) , lastSentAddr = > ( others = > ' 0 ' ) , nextSentAddr = > ( others = > ' 0 ' ) , lastAckSeqN = > ( others = > ' 0 ' ) , bufferFull = > ' 0 ' , bufferEmpty = > ' 1 ' , windowArray = > ( 0 to 2 ** WINDOW_ADDR_SIZE_G- 1 = > WINDOW_INIT_C ) , ackErr = > ' 0 ' , ackState = > IDLE_S , txAckState = > ( others = > ' 0 ' ) , rxSegmentAddr = > ( others = > ' 0 ' ) , rxSegmentWe = > ' 0 ' , rxBufferAddr = > ( others = > ' 0 ' ) , sndData = > ' 0 ' , lenErr = > ' 0 ' , appBusy = > ' 0 ' , appDrop = > ' 0 ' , appSsiMaster = > SSI_MASTER_INIT_C , appSsiSlave = > SSI_SLAVE_NOTRDY_C , appState = > IDLE_S , txAppState = > ( others = > ' 0 ' ) , nextSeqN = > ( others = > ' 0 ' ) , seqN = > ( others = > ' 0 ' ) , txHeaderAddr = > ( others = > ' 0 ' ) , txSegmentAddr = > ( others = > ' 0 ' ) , txBufferAddr = > ( others = > ' 0 ' ) , synH = > ' 0 ' , ackH = > ' 0 ' , rstH = > ' 0 ' , nullH = > ' 0 ' , dataH = > ' 0 ' , dataD = > ' 0 ' , resend = > ' 0 ' , ackSndData = > ' 0 ' , txRdy = > ' 0 ' , buffWe = > ' 0 ' , buffSent = > ' 0 ' , chkEn = > ' 0 ' , chkStb = > ' 0 ' , injectFaultD1 = > ' 0 ' , injectFaultReg = > ' 0 ' , tspSsiMaster = > SSI_MASTER_INIT_C , tspSsiSlave = > SSI_SLAVE_NOTRDY_C , tspState = > INIT_S , txTspState = > ( others = > ' 0 ' ) )

Types

TspStateType  ( INIT_S , DISS_CONN_S , CONN_S , SYN_H_S , ACK_H_S , RST_H_S , NULL_H_S , DATA_H_S , DATA_S , DATA_SENT_S , RST_WE_S , DATA_WE_S , NULL_WE_S , RESEND_INIT_S , RESEND_H_S , RESEND_DATA_S , RESEND_PP_S )
AppStateType  ( IDLE_S , WAIT_SOF_S , SEG_RCV_S , SEG_RDY_S , SEG_LEN_ERR )
AckStateType  ( IDLE_S , ERR_S , ACK_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
s_chksum  slv ( chksum_i )
s_headerAndChksum  slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )

Records

RegType 

The documentation for this design unit was generated from the following files: