SugoiManagerCore.mapping Architecture Reference

Architecture >> SugoiManagerCore::mapping

Signals
readMaster	AxiLiteReadMasterType
readSlave	AxiLiteReadSlaveType
writeMaster	AxiLiteWriteMasterType
writeSlave	AxiLiteWriteSlaveType
rx	sl
rxEncodeValid	sl
rxEncodeData	slv ( 9 downto 0 )
rxSlip	sl
gearboxAligned	sl
errorDet	sl
dlyLoad	sl
dlyCfg	slv ( 8 downto 0 )
enUsrDlyCfg	sl
usrDlyCfg	slv ( 8 downto 0 )
eyeWidth	slv ( 8 downto 0 )
bypFirstBerDet	sl
minEyeWidth	slv ( 7 downto 0 )
lockingCntCfg	slv ( 23 downto 0 )
rxDecodeValid	sl
rxDecodeData	slv ( 7 downto 0 )
rxDecodeDataK	sl
rxCodeErr	sl
rxDispErr	sl
txStrobe	sl
txDecodeData	slv ( 7 downto 0 )
txDecodeDataK	sl
txEncodeValid	sl
txEncodeData	slv ( 9 downto 0 )
tx	sl
polarityRx	sl
polarityTx	sl
disableClk	sl
disableTx	sl

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_rx	SugoiManagerRx <Entity SugoiManagerRx>
u_gearboxaligner	SelectIoRxGearboxAligner <Entity SelectIoRxGearboxAligner>
u_deserializer	Gearbox <Entity Gearbox>
u_decode	Decoder8b10b <Entity Decoder8b10b>
u_fsm	SugoiManagerFsm <Entity SugoiManagerFsm>
u_encode	Encoder8b10b <Entity Encoder8b10b>
u_serializer	Gearbox <Entity Gearbox>
u_sugoitx	OutputBufferReg <Entity OutputBufferReg>
u_sugoiclk	ClkOutBufDiff <Entity ClkOutBufDiff>
u_sugoiclk	ClkOutBufSingle <Entity ClkOutBufSingle>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_rx	SugoiManagerRx <Entity SugoiManagerRx>
u_gearboxaligner	SelectIoRxGearboxAligner <Entity SelectIoRxGearboxAligner>
u_deserializer	Gearbox <Entity Gearbox>
u_decode	Decoder8b10b <Entity Decoder8b10b>
u_fsm	SugoiManagerFsm <Entity SugoiManagerFsm>
u_encode	Encoder8b10b <Entity Encoder8b10b>
u_serializer	Gearbox <Entity Gearbox>
u_sugoitx	OutputBufferReg <Entity OutputBufferReg>
u_sugoiclk	ClkOutBufDiff <Entity ClkOutBufDiff>
u_sugoiclk	ClkOutBufSingle <Entity ClkOutBufSingle>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SugoiManagerCore.vhd
• protocols/sugoi/rtl/SugoiManagerCore.vhd