Decoder8b10b Entity Reference

Inheritance diagram for Decoder8b10b:

Entities
Decoder8b10b.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
Code8b10bPkg	Package <Code8b10bPkg>

Generics
TPD_G	time := 1 ns
NUM_BYTES_G	positive := 2
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Ports
clk	in	sl
clkEn	in	sl := ' 1 '
rst	in	sl := not RST_POLARITY_G
validIn	in	sl := ' 1 '
dataIn	in	slv ( NUM_BYTES_G* 10 - 1 downto 0 )
dataOut	out	slv ( NUM_BYTES_G* 8 - 1 downto 0 )
dataKOut	out	slv ( NUM_BYTES_G- 1 downto 0 )
validOut	out	sl
codeErr	out	slv ( NUM_BYTES_G- 1 downto 0 )
dispErr	out	slv ( NUM_BYTES_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Decoder8b10b.vhd
• protocols/line-codes/rtl/Decoder8b10b.vhd