Decoder8b10b.rtl Architecture Reference

Architecture >> Decoder8b10b::rtl

Processes
comb	( dataIn , r , rst , validIn )
seq	( clk , rst )
comb	( dataIn , r , rst , validIn )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( runDisp = > ' 0 ' , dataOut = > ( others = > ' 0 ' ) , dataKOut = > ( others = > ' 0 ' ) , validOut = > ' 0 ' , codeErr = > ( others = > ' 0 ' ) , dispErr = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Decoder8b10b.vhd
• protocols/line-codes/rtl/Decoder8b10b.vhd