OutputBufferReg Entity Reference

Inheritance diagram for OutputBufferReg:

Entities
OutputBufferReg.mapping	architecture
OutputBufferReg.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
DIFF_PAIR_G	boolean := false
DDR_CLK_EDGE_G	string := " SAME_EDGE "
INIT_G	bit := ' 0 '
SRTYPE_G	string := " SYNC "

Ports
I	in	sl := ' 0 '
C	in	sl := ' 0 '
CE	in	sl := ' 1 '
R	in	sl := ' 0 '
SR	in	sl := ' 0 '
S	in	sl := ' 0 '
T	in	sl := ' 0 '
inv	in	sl := ' 0 '
dly	in	sl := ' 0 '
O	out	sl := ' 0 '
OB	out	sl := ' 1 '

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/OutputBufferRegDummy.vhd
• xilinx/7Series/general/rtl/OutputBufferReg.vhd
• xilinx/dummy/OutputBufferRegDummy.vhd
• xilinx/UltraScale/general/rtl/OutputBufferReg.vhd