OutputBufferReg.rtl Architecture Reference

Architecture >> OutputBufferReg::rtl

Processes
PROCESS_374	( C )
PROCESS_445	( C )

Signals
mask	sl := ' 0 '
maskDly	sl := ' 0 '
D1	sl := ' 0 '
D2	sl := ' 0 '
outputSig	sl := ' 0 '

Instantiations
u_oddr	oddr
u_obufds	obuft
u_obufds	obuftds
u_oddr	oddre1
u_obufds	obuft
u_obufds	obuftds

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The documentation for this design unit was generated from the following files:

• xilinx/7Series/general/rtl/OutputBufferReg.vhd
• xilinx/UltraScale/general/rtl/OutputBufferReg.vhd