ClkOutBufDiff Entity Reference

Inheritance diagram for ClkOutBufDiff:

Entities
ClkOutBufDiff.mapping	architecture
ClkOutBufDiff.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " 7SERIES "
RST_POLARITY_G	sl := ' 1 '
INVERT_G	boolean := false

Ports
rstIn	in	sl := not RST_POLARITY_G
outEnL	in	sl := ' 0 '
clkIn	in	sl := ' 0 '
clkOutP	out	sl := ' 0 '
clkOutN	out	sl := ' 1 '

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/ClkOutBufDiffDummy.vhd
• xilinx/dummy/ClkOutBufDiffDummy.vhd
• xilinx/general/rtl/ClkOutBufDiff.vhd