SugoiManagerCore Entity Reference

Inheritance diagram for SugoiManagerCore:

Collaboration diagram for SugoiManagerCore:

Entities
SugoiManagerCore.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
RST_ASYNC_G	boolean := false
DIFF_PAIR_G	boolean := true
GEN_TX_DRIVER_G	boolean := true
GEN_CLK_DRIVER_G	boolean := true
COMMON_CLK_G	boolean := false
NUM_ADDR_BITS_G	positive
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
DEVICE_FAMILY_G	string
IODELAY_GROUP_G	string := " DESER_GROUP "
REF_FREQ_G	real := 300 . 0

Ports
sugoiRxP	in	sl
sugoiRxN	in	sl
sugoiTxP	out	sl
sugoiTxN	out	sl
sugoiClkP	out	sl
sugoiClkN	out	sl
timingClk	in	sl
timingRst	in	sl
sugoiGlobalRst	in	sl
sugoiOpCode	in	slv ( 7 downto 0 )
sugoiStrobe	out	sl
sugoiLinkup	out	sl
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SugoiManagerCore.vhd
• protocols/sugoi/rtl/SugoiManagerCore.vhd