Architecture >> FifoAsync::mapping

Constants
SYNC_INIT_C	slv ( SYNC_STAGES_G- 1 downto 0 ) := ( others = > ' 0 ' )
GRAY_INIT_C	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

Signals
wrRst	sl := ' 0 '
rdRst	sl := ' 0 '
rdRdy	sl := ' 0 '
rdIndex	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
wrRdy	sl := ' 0 '
wrIndex	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
rdRdySync	sl := ' 0 '
rdIndexSync	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
wrRdySync	sl := ' 0 '
wrIndexSync	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
wea	sl := ' 0 '
addra	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
addrb	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
enb	sl := ' 0 '
regceb	sl := ' 0 '
localDout	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
localValid	sl := ' 0 '
localRdEn	sl := ' 0 '

Instantiations
u_wrrst	RstSync <Entity RstSync>
u_rdindex	SynchronizerVector <Entity SynchronizerVector>
u_rdrdy	Synchronizer <Entity Synchronizer>
u_wr_fsm	FifoWrFsm <Entity FifoWrFsm>
u_rdrst	RstSync <Entity RstSync>
u_wrindex	SynchronizerVector <Entity SynchronizerVector>
u_wrrdy	Synchronizer <Entity Synchronizer>
u_rd_fsm	FifoRdFsm <Entity FifoRdFsm>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>
u_wrrst	RstSync <Entity RstSync>
u_rdindex	SynchronizerVector <Entity SynchronizerVector>
u_rdrdy	Synchronizer <Entity Synchronizer>
u_wr_fsm	FifoWrFsm <Entity FifoWrFsm>
u_rdrst	RstSync <Entity RstSync>
u_wrindex	SynchronizerVector <Entity SynchronizerVector>
u_wrrdy	Synchronizer <Entity Synchronizer>
u_rd_fsm	FifoRdFsm <Entity FifoRdFsm>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>

The documentation for this design unit was generated from the following files:

Constants

Signals