ClinkTop.rtl Architecture Reference

Architecture >> ClinkTop::rtl

Constants
NUM_AXIL_MASTERS_C	natural := 4
MAIN_INDEX_C	natural := 0
DRP0_INDEX_C	natural := 1
DRP1_INDEX_C	natural := 2
DRP2_INDEX_C	natural := 3
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 14 , 12 )

Signals
intReadMaster	AxiLiteReadMasterType
intReadSlave	AxiLiteReadSlaveType
intWriteMaster	AxiLiteWriteMasterType
intWriteSlave	AxiLiteWriteSlaveType
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
chanConfig	ClChanConfigArray ( 1 downto 0 )
linkConfig	ClLinkConfigType
chanStatus	ClChanStatusArray ( 1 downto 0 ) := ( others = > CL_CHAN_STATUS_INIT_C )
linkStatus	ClLinkStatusArray ( 2 downto 0 ) := ( others = > CL_LINK_STATUS_INIT_C )
parData	Slv28Array ( 2 downto 0 )
parValid	slv ( 2 downto 0 )
frameReady	slv ( 1 downto 0 )

Attributes
IODELAY_GROUP	string
IODELAY_GROUP	label is " CLINK_CORE "

Instantiations
u_idelayctrl	idelayctrl
u_axilasync	AxiLiteAsync <Entity AxiLiteAsync>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_clinkreg	ClinkReg <Entity ClinkReg>
u_cbl0half0	ClinkCtrl <Entity ClinkCtrl>
u_cbl0half1	ClinkData <Entity ClinkData>
u_cbl1half0	ClinkCtrl <Entity ClinkCtrl>
u_unuseddrp	AxiDualPortRam <Entity AxiDualPortRam>
u_cbl1half0	ClinkData <Entity ClinkData>
u_serout	obufds
u_cbl1half1	ClinkData <Entity ClinkData>
u_framer0	ClinkFraming <Entity ClinkFraming>
u_framer1	ClinkFraming <Entity ClinkFraming>

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkTop.vhd