ClinkTop Entity Reference

Inheritance diagram for ClinkTop:

Collaboration diagram for ClinkTop:

Entities
ClinkTop.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
ClinkPkg	Package <ClinkPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
vcomponents

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " 7SERIES "
CHAN_COUNT_G	integer range 1 to 2 := 1
UART_READY_EN_G	boolean := true
COMMON_AXIL_CLK_G	boolean := false
COMMON_DATA_CLK_G	boolean := false
DATA_AXIS_CONFIG_G	AxiStreamConfigType
UART_AXIS_CONFIG_G	AxiStreamConfigType
AXIL_BASE_ADDR_G	slv ( 31 downto 0 )

Ports
cbl0Half0P	inout	slv ( 4 downto 0 )
cbl0Half0M	inout	slv ( 4 downto 0 )
cbl0Half1P	inout	slv ( 4 downto 0 )
cbl0Half1M	inout	slv ( 4 downto 0 )
cbl0SerP	out	sl
cbl0SerM	out	sl
cbl1Half0P	inout	slv ( 4 downto 0 )
cbl1Half0M	inout	slv ( 4 downto 0 )
cbl1Half1P	inout	slv ( 4 downto 0 )
cbl1Half1M	inout	slv ( 4 downto 0 )
cbl1SerP	out	sl
cbl1SerM	out	sl
dlyClk	in	sl
dlyRst	in	sl
sysClk	in	sl
sysRst	in	sl
camCtrl	in	Slv4Array ( CHAN_COUNT_G- 1 downto 0 )
camStatus	out	ClChanStatusArray ( 1 downto 0 )
dataClk	in	sl
dataRst	in	sl
dataMasters	out	AxiStreamMasterArray ( CHAN_COUNT_G- 1 downto 0 )
dataSlaves	in	AxiStreamSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
uartClk	in	sl
uartRst	in	sl
sUartMasters	in	AxiStreamMasterArray ( CHAN_COUNT_G- 1 downto 0 )
sUartSlaves	out	AxiStreamSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
sUartCtrls	out	AxiStreamCtrlArray ( CHAN_COUNT_G- 1 downto 0 )
mUartMasters	out	AxiStreamMasterArray ( CHAN_COUNT_G- 1 downto 0 )
mUartSlaves	in	AxiStreamSlaveArray ( CHAN_COUNT_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkTop.vhd