ClinkCtrl Entity Reference

Inheritance diagram for ClinkCtrl:

Collaboration diagram for ClinkCtrl:

Entities
ClinkCtrl.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
ClinkPkg	Package <ClinkPkg>
AxiStreamPkg	Package <AxiStreamPkg>
vcomponents

Generics
TPD_G	time := 1 ns
INV_34_G	boolean := false
UART_READY_EN_G	boolean := true
UART_AXIS_CONFIG_G	AxiStreamConfigType

Ports
cblHalfP	inout	slv ( 4 downto 0 )
cblHalfM	inout	slv ( 4 downto 0 )
cblSerP	out	sl
cblSerM	out	sl
dlyClk	in	sl
dlyRst	in	sl
sysClk	in	sl
sysRst	in	sl
camCtrl	in	slv ( 3 downto 0 )
chanConfig	in	ClChanConfigType
uartClk	in	sl
uartRst	in	sl
sUartMaster	in	AxiStreamMasterType
sUartSlave	out	AxiStreamSlaveType
sUartCtrl	out	AxiStreamCtrlType
mUartMaster	out	AxiStreamMasterType
mUartSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkCtrl.vhd