Loading...
Searching...
No Matches
ClinkReg Entity Reference
Inheritance diagram for ClinkReg:Entities | |
| ClinkReg.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| ClinkPkg | Package <ClinkPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| CHAN_COUNT_G | integer range 1 to 2 := 1 |
Ports | ||
| chanStatus | in | ClChanStatusArray ( 1 downto 0 ) |
| linkStatus | in | ClLinkStatusArray ( 2 downto 0 ) |
| chanConfig | out | ClChanConfigArray ( 1 downto 0 ) |
| linkConfig | out | ClLinkConfigType |
| sysClk | in | sl |
| sysRst | in | sl |
| axilReadMaster | in | AxiLiteReadMasterType |
| axilReadSlave | out | AxiLiteReadSlaveType |
| axilWriteMaster | in | AxiLiteWriteMasterType |
| axilWriteSlave | out | AxiLiteWriteSlaveType |
The documentation for this design unit was generated from the following file:
- protocols/clink/rtl/ClinkReg.vhd
