ClinkReg.rtl Architecture Reference

Architecture >> ClinkReg::rtl

Processes
comb	( axilReadMaster , axilWriteMaster , chanStatus , linkStatus , r , sysRst )
seq	( sysClk )

Constants
REG_INIT_C	RegType := ( locked = > " 000 " , lockCnt = > ( others = > x " 00 " ) , chanConfig = > ( others = > CL_CHAN_CONFIG_INIT_C ) , linkConfig = > CL_LINK_CONFIG_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkReg.vhd