SURF  1.0
TenGigEthGthUltraScale.vhd
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1 -------------------------------------------------------------------------------
2 -- File : TenGigEthGthUltraScale.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-04-08
5 -- Last update: 2017-06-22
6 -------------------------------------------------------------------------------
7 -- Description: 10GBASE-R Ethernet for GTH Ultra Scale
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 use work.AxiStreamPkg.all;
23 use work.AxiLitePkg.all;
24 use work.TenGigEthPkg.all;
25 use work.EthMacPkg.all;
26 
27 --! @see entity
28  --! @ingroup ethernet_TenGigEthCore_gthUltraScale
29 entity TenGigEthGthUltraScale is
30  generic (
31  TPD_G : time := 1 ns;
32  REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz
33  -- AXI-Lite Configurations
34  EN_AXI_REG_G : boolean := false;
35  AXI_ERROR_RESP_G : slv(1 downto 0) := AXI_RESP_SLVERR_C;
36  -- AXI Streaming Configurations
37  AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C);
38  port (
39  -- Local Configurations
40  localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C;
41  -- Streaming DMA Interface
42  dmaClk : in sl;
43  dmaRst : in sl;
44  dmaIbMaster : out AxiStreamMasterType;
45  dmaIbSlave : in AxiStreamSlaveType;
46  dmaObMaster : in AxiStreamMasterType;
47  dmaObSlave : out AxiStreamSlaveType;
48  -- Slave AXI-Lite Interface
49  axiLiteClk : in sl := '0';
50  axiLiteRst : in sl := '0';
51  axiLiteReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C;
52  axiLiteReadSlave : out AxiLiteReadSlaveType;
53  axiLiteWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
54  axiLiteWriteSlave : out AxiLiteWriteSlaveType;
55  -- SFP+ Ports
56  sigDet : in sl := '1';
57  txFault : in sl := '0';
58  txDisable : out sl;
59  -- Misc. Signals
60  extRst : in sl;
61  coreClk : in sl;
62  phyClk : out sl;
63  phyRst : out sl;
64  phyReady : out sl;
65  -- Transceiver Debug Interface
66  gtTxPreCursor : in slv(4 downto 0) := "00000";
67  gtTxPostCursor : in slv(4 downto 0) := "00000";
68  gtTxDiffCtrl : in slv(3 downto 0) := "1110";
69  gtRxPolarity : in sl := '0';
70  gtTxPolarity : in sl := '0';
71  -- Quad PLL Ports
72  qplllock : in sl;
73  qplloutclk : in sl;
74  qplloutrefclk : in sl;
75  qpllRst : out sl;
76  -- MGT Ports
77  gtTxP : out sl;
78  gtTxN : out sl;
79  gtRxP : in sl;
80  gtRxN : in sl);
81 end TenGigEthGthUltraScale;
82 
83 architecture mapping of TenGigEthGthUltraScale is
84 
85  component TenGigEthGthUltraScale156p25MHzCore
86  port (
87  dclk : in std_logic;
88  rxrecclk_out : out std_logic;
89  coreclk : in std_logic;
90  txusrclk : in std_logic;
91  txusrclk2 : in std_logic;
92  txoutclk : out std_logic;
93  areset : in std_logic;
94  areset_coreclk : in std_logic;
95  gttxreset : in std_logic;
96  gtrxreset : in std_logic;
97  sim_speedup_control : in std_logic;
98  txuserrdy : in std_logic;
99  qpll0lock : in std_logic;
100  qpll0outclk : in std_logic;
101  qpll0outrefclk : in std_logic;
102  qpll0reset : out std_logic;
103  reset_tx_bufg_gt : out std_logic;
104  reset_counter_done : in std_logic;
105  gt_eyescanreset : in std_logic;
106  gt_eyescantrigger : in std_logic;
107  gt_rxcdrhold : in std_logic;
108  gt_txprbsforceerr : in std_logic;
109  gt_txpolarity : in std_logic;
110  gt_rxpolarity : in std_logic;
111  gt_rxrate : in std_logic_vector (2 downto 0);
112  gt_txoutclksel : in std_logic_vector (2 downto 0);
113  gt_txpcsreset : in std_logic;
114  gt_txpmareset : in std_logic;
115  gt_rxpmareset : in std_logic;
116  gt_rxdfelpmreset : in std_logic;
117  gt_txprecursor : in std_logic_vector (4 downto 0);
118  gt_txpostcursor : in std_logic_vector (4 downto 0);
119  gt_txdiffctrl : in std_logic_vector (3 downto 0);
120  gt_rxlpmen : in std_logic;
121  gt_pcsrsvdin : in std_logic_vector (15 downto 0);
122  gt_eyescandataerror : out std_logic;
123  gt_txbufstatus : out std_logic_vector (1 downto 0);
124  gt_txresetdone : out std_logic;
125  gt_rxpmaresetdone : out std_logic;
126  gt_rxresetdone : out std_logic;
127  gt_rxbufstatus : out std_logic_vector (2 downto 0);
128  gt_rxprbserr : out std_logic;
129  gt_dmonitorout : out std_logic_vector (16 downto 0);
130  xgmii_txd : in std_logic_vector (63 downto 0);
131  xgmii_txc : in std_logic_vector (7 downto 0);
132  xgmii_rxd : out std_logic_vector (63 downto 0);
133  xgmii_rxc : out std_logic_vector (7 downto 0);
134  txp : out std_logic;
135  txn : out std_logic;
136  rxp : in std_logic;
137  rxn : in std_logic;
138  configuration_vector : in std_logic_vector (535 downto 0);
139  status_vector : out std_logic_vector (447 downto 0);
140  core_status : out std_logic_vector (7 downto 0);
141  tx_resetdone : out std_logic;
142  rx_resetdone : out std_logic;
143  signal_detect : in std_logic;
144  tx_fault : in std_logic;
145  drp_req : out std_logic;
146  drp_gnt : in std_logic;
147  core_to_gt_drpen : out std_logic;
148  core_to_gt_drpwe : out std_logic;
149  core_to_gt_drpaddr : out std_logic_vector (15 downto 0);
150  core_to_gt_drpdi : out std_logic_vector (15 downto 0);
151  core_to_gt_drprdy : in std_logic;
152  core_to_gt_drpdo : in std_logic_vector (15 downto 0);
153  gt_drpen : in std_logic;
154  gt_drpwe : in std_logic;
155  gt_drpaddr : in std_logic_vector (15 downto 0);
156  gt_drpdi : in std_logic_vector (15 downto 0);
157  gt_drprdy : out std_logic;
158  gt_drpdo : out std_logic_vector (15 downto 0);
159  pma_pmd_type : in std_logic_vector (2 downto 0);
160  tx_disable : out std_logic
161  );
162  end component;
163 
164  component TenGigEthGthUltraScale312p5MHzCore
165  port (
166  dclk : in std_logic;
167  rxrecclk_out : out std_logic;
168  coreclk : in std_logic;
169  txusrclk : in std_logic;
170  txusrclk2 : in std_logic;
171  txoutclk : out std_logic;
172  areset : in std_logic;
173  areset_coreclk : in std_logic;
174  gttxreset : in std_logic;
175  gtrxreset : in std_logic;
176  sim_speedup_control : in std_logic;
177  txuserrdy : in std_logic;
178  qpll0lock : in std_logic;
179  qpll0outclk : in std_logic;
180  qpll0outrefclk : in std_logic;
181  qpll0reset : out std_logic;
182  reset_tx_bufg_gt : out std_logic;
183  reset_counter_done : in std_logic;
184  gt_eyescanreset : in std_logic;
185  gt_eyescantrigger : in std_logic;
186  gt_rxcdrhold : in std_logic;
187  gt_txprbsforceerr : in std_logic;
188  gt_txpolarity : in std_logic;
189  gt_rxpolarity : in std_logic;
190  gt_rxrate : in std_logic_vector (2 downto 0);
191  gt_txoutclksel : in std_logic_vector (2 downto 0);
192  gt_txpcsreset : in std_logic;
193  gt_txpmareset : in std_logic;
194  gt_rxpmareset : in std_logic;
195  gt_rxdfelpmreset : in std_logic;
196  gt_txprecursor : in std_logic_vector (4 downto 0);
197  gt_txpostcursor : in std_logic_vector (4 downto 0);
198  gt_txdiffctrl : in std_logic_vector (3 downto 0);
199  gt_rxlpmen : in std_logic;
200  gt_pcsrsvdin : in std_logic_vector (15 downto 0);
201  gt_eyescandataerror : out std_logic;
202  gt_txbufstatus : out std_logic_vector (1 downto 0);
203  gt_txresetdone : out std_logic;
204  gt_rxpmaresetdone : out std_logic;
205  gt_rxresetdone : out std_logic;
206  gt_rxbufstatus : out std_logic_vector (2 downto 0);
207  gt_rxprbserr : out std_logic;
208  gt_dmonitorout : out std_logic_vector (16 downto 0);
209  xgmii_txd : in std_logic_vector (63 downto 0);
210  xgmii_txc : in std_logic_vector (7 downto 0);
211  xgmii_rxd : out std_logic_vector (63 downto 0);
212  xgmii_rxc : out std_logic_vector (7 downto 0);
213  txp : out std_logic;
214  txn : out std_logic;
215  rxp : in std_logic;
216  rxn : in std_logic;
217  configuration_vector : in std_logic_vector (535 downto 0);
218  status_vector : out std_logic_vector (447 downto 0);
219  core_status : out std_logic_vector (7 downto 0);
220  tx_resetdone : out std_logic;
221  rx_resetdone : out std_logic;
222  signal_detect : in std_logic;
223  tx_fault : in std_logic;
224  drp_req : out std_logic;
225  drp_gnt : in std_logic;
226  core_to_gt_drpen : out std_logic;
227  core_to_gt_drpwe : out std_logic;
228  core_to_gt_drpaddr : out std_logic_vector (15 downto 0);
229  core_to_gt_drpdi : out std_logic_vector (15 downto 0);
230  core_to_gt_drprdy : in std_logic;
231  core_to_gt_drpdo : in std_logic_vector (15 downto 0);
232  gt_drpen : in std_logic;
233  gt_drpwe : in std_logic;
234  gt_drpaddr : in std_logic_vector (15 downto 0);
235  gt_drpdi : in std_logic_vector (15 downto 0);
236  gt_drprdy : out std_logic;
237  gt_drpdo : out std_logic_vector (15 downto 0);
238  pma_pmd_type : in std_logic_vector (2 downto 0);
239  tx_disable : out std_logic
240  );
241  end component;
242 
243  signal mAxiReadMaster : AxiLiteReadMasterType;
244  signal mAxiReadSlave : AxiLiteReadSlaveType;
245  signal mAxiWriteMaster : AxiLiteWriteMasterType;
246  signal mAxiWriteSlave : AxiLiteWriteSlaveType;
247 
248  signal phyRxd : slv(63 downto 0);
249  signal phyRxc : slv(7 downto 0);
250  signal phyTxd : slv(63 downto 0);
251  signal phyTxc : slv(7 downto 0);
252 
253  signal areset : sl;
254  signal coreRst : sl;
255  signal phyClock : sl;
256  signal phyReset : sl;
257  signal txClk322 : sl;
258  signal txUsrClk : sl;
259  signal txUsrClk2 : sl;
260  signal txUsrRdy : sl;
261  signal txBufgGtRst : sl;
262 
263  signal drpReqGnt : sl;
264  signal drpEn : sl;
265  signal drpWe : sl;
266  signal drpAddr : slv(15 downto 0);
267  signal drpDi : slv(15 downto 0);
268  signal drpRdy : sl;
269  signal drpDo : slv(15 downto 0);
270 
271  signal configurationVector : slv(535 downto 0) := (others => '0');
272 
273  signal config : TenGigEthConfig;
274  signal status : TenGigEthStatus;
275 
276  signal macRxAxisMaster : AxiStreamMasterType;
277  signal macRxAxisCtrl : AxiStreamCtrlType;
278  signal macTxAxisMaster : AxiStreamMasterType;
279  signal macTxAxisSlave : AxiStreamSlaveType;
280 
281 begin
282 
283  phyClk <= phyClock;
284  phyRst <= phyReset;
285  phyReady <= status.phyReady;
286  areset <= extRst or config.softRst;
287  status.qplllock <= qplllock;
288 
289  ------------------
290  -- Synchronization
291  ------------------
292  U_AxiLiteAsync : entity work.AxiLiteAsync
293  generic map (
294  TPD_G => TPD_G)
295  port map (
296  -- Slave Port
297  sAxiClk => axiLiteClk,
298  sAxiClkRst => axiLiteRst,
299  sAxiReadMaster => axiLiteReadMaster,
300  sAxiReadSlave => axiLiteReadSlave,
301  sAxiWriteMaster => axiLiteWriteMaster,
302  sAxiWriteSlave => axiLiteWriteSlave,
303  -- Master Port
304  mAxiClk => phyClock,
305  mAxiClkRst => phyReset,
306  mAxiReadMaster => mAxiReadMaster,
307  mAxiReadSlave => mAxiReadSlave,
308  mAxiWriteMaster => mAxiWriteMaster,
309  mAxiWriteSlave => mAxiWriteSlave);
310 
311  txDisable <= status.txDisable;
312 
313  U_Sync : entity work.SynchronizerVector
314  generic map (
315  TPD_G => TPD_G,
316  WIDTH_G => 3)
317  port map (
318  clk => phyClock,
319  -- Input
320  dataIn(0) => sigDet,
321  dataIn(1) => txFault,
322  dataIn(2) => txUsrRdy,
323  -- Output
324  dataOut(0) => status.sigDet,
325  dataOut(1) => status.txFault,
326  dataOut(2) => status.txUsrRdy);
327 
328  --------------------
329  -- Ethernet MAC core
330  --------------------
331  U_MAC : entity work.EthMacTop
332  generic map (
333  TPD_G => TPD_G,
334  PHY_TYPE_G => "XGMII",
335  PRIM_CONFIG_G => AXIS_CONFIG_G)
336  port map (
337  -- Primary Interface
338  primClk => dmaClk,
339  primRst => dmaRst,
340  ibMacPrimMaster => dmaObMaster,
341  ibMacPrimSlave => dmaObSlave,
342  obMacPrimMaster => dmaIbMaster,
343  obMacPrimSlave => dmaIbSlave,
344  -- Ethernet Interface
345  ethClk => phyClock,
346  ethRst => phyReset,
347  ethConfig => config.macConfig,
348  ethStatus => status.macStatus,
349  phyReady => status.phyReady,
350  -- XGMII PHY Interface
351  xgmiiRxd => phyRxd,
352  xgmiiRxc => phyRxc,
353  xgmiiTxd => phyTxd,
354  xgmiiTxc => phyTxc);
355 
356  -----------------
357  -- 10GBASE-R core
358  -----------------
359  GEN_156p25MHz : if (REF_CLK_FREQ_G = 156.25E+6) generate
360  U_TenGigEthGthUltraScaleCore : TenGigEthGthUltraScale156p25MHzCore
361  port map (
362  -- Clocks and Resets
363  coreclk => coreclk,
364  dclk => coreclk,
365  txusrclk => txusrclk,
366  txusrclk2 => txusrclk2,
367  txoutclk => txClk322,
368  areset_coreclk => coreRst,
369  txuserrdy => txUsrRdy,
370  rxrecclk_out => open,
371  areset => areset,
372  gttxreset => status.gtTxRst,
373  gtrxreset => status.gtRxRst,
374  reset_tx_bufg_gt => txBufgGtRst,
375  reset_counter_done => status.rstCntDone,
376  -- Quad PLL Interface
377  qpll0lock => status.qplllock,
378  qpll0outclk => qplloutclk,
379  qpll0outrefclk => qplloutrefclk,
380  qpll0reset => qpllRst,
381  -- MGT Ports
382  txp => gtTxP,
383  txn => gtTxN,
384  rxp => gtRxP,
385  rxn => gtRxN,
386  -- PHY Interface
387  xgmii_txd => phyTxd,
388  xgmii_txc => phyTxc,
389  xgmii_rxd => phyRxd,
390  xgmii_rxc => phyRxc,
391  -- Configuration and Status
392  sim_speedup_control => '0',
393  configuration_vector => configurationVector,
394  status_vector => open,
395  core_status => status.core_status,
396  tx_resetdone => status.txRstdone,
397  rx_resetdone => status.rxRstdone,
398  signal_detect => status.sigDet,
399  tx_fault => status.txFault,
400  tx_disable => status.txDisable,
401  pma_pmd_type => config.pma_pmd_type,
402  -- DRP interface
403  -- Note: If no arbitration is required on the GT DRP ports
404  -- then connect REQ to GNT and connect other signals i <= o;
405  drp_req => drpReqGnt,
406  drp_gnt => drpReqGnt,
407  core_to_gt_drpen => drpEn,
408  core_to_gt_drpwe => drpWe,
409  core_to_gt_drpaddr => drpAddr,
410  core_to_gt_drpdi => drpDi,
411  gt_drprdy => drpRdy,
412  gt_drpdo => drpDo,
413  gt_drpen => drpEn,
414  gt_drpwe => drpWe,
415  gt_drpaddr => drpAddr,
416  gt_drpdi => drpDi,
417  core_to_gt_drprdy => drpRdy,
418  core_to_gt_drpdo => drpDo,
419  -- Transceiver Debug Interface
420  gt_txpcsreset => extRst,
421  gt_txpmareset => '0',
422  gt_rxpmareset => '0',
423  gt_txresetdone => open,
424  gt_rxresetdone => open,
425  gt_rxpmaresetdone => open,
426  gt_txbufstatus => open,
427  gt_rxbufstatus => open,
428  gt_rxrate => (others => '0'),
429  gt_eyescantrigger => '0',
430  gt_eyescanreset => '0',
431  gt_eyescandataerror => open,
432  gt_rxpolarity => gtRxPolarity,
433  gt_txpolarity => gtTxPolarity,
434  gt_rxdfelpmreset => '0',
435  gt_txprbsforceerr => '0',
436  gt_rxprbserr => open,
437  gt_rxcdrhold => '0',
438  gt_dmonitorout => open,
439  gt_rxlpmen => '0',
440  gt_txprecursor => gtTxPreCursor,
441  gt_txpostcursor => gtTxPostCursor,
442  gt_txdiffctrl => gtTxDiffCtrl,
443  gt_pcsrsvdin => (others => '0'),
444  gt_txoutclksel => "101");
445  end generate;
446  GEN_312p5MHz : if (REF_CLK_FREQ_G = 312.50E+6) generate
447  U_TenGigEthGthUltraScaleCore : TenGigEthGthUltraScale312p5MHzCore
448  port map (
449  -- Clocks and Resets
450  coreclk => coreclk,
451  dclk => phyClock,
452  txusrclk => txusrclk,
453  txusrclk2 => txusrclk2,
454  txoutclk => txClk322,
455  areset_coreclk => coreRst,
456  txuserrdy => txUsrRdy,
457  rxrecclk_out => open,
458  areset => areset,
459  gttxreset => status.gtTxRst,
460  gtrxreset => status.gtRxRst,
461  reset_tx_bufg_gt => txBufgGtRst,
462  reset_counter_done => status.rstCntDone,
463  -- Quad PLL Interface
464  qpll0lock => status.qplllock,
465  qpll0outclk => qplloutclk,
466  qpll0outrefclk => qplloutrefclk,
467  qpll0reset => qpllRst,
468  -- MGT Ports
469  txp => gtTxP,
470  txn => gtTxN,
471  rxp => gtRxP,
472  rxn => gtRxN,
473  -- PHY Interface
474  xgmii_txd => phyTxd,
475  xgmii_txc => phyTxc,
476  xgmii_rxd => phyRxd,
477  xgmii_rxc => phyRxc,
478  -- Configuration and Status
479  sim_speedup_control => '0',
480  configuration_vector => configurationVector,
481  status_vector => open,
482  core_status => status.core_status,
483  tx_resetdone => status.txRstdone,
484  rx_resetdone => status.rxRstdone,
485  signal_detect => status.sigDet,
486  tx_fault => status.txFault,
487  tx_disable => status.txDisable,
488  pma_pmd_type => config.pma_pmd_type,
489  -- DRP interface
490  -- Note: If no arbitration is required on the GT DRP ports
491  -- then connect REQ to GNT and connect other signals i <= o;
492  drp_req => drpReqGnt,
493  drp_gnt => drpReqGnt,
494  core_to_gt_drpen => drpEn,
495  core_to_gt_drpwe => drpWe,
496  core_to_gt_drpaddr => drpAddr,
497  core_to_gt_drpdi => drpDi,
498  gt_drprdy => drpRdy,
499  gt_drpdo => drpDo,
500  gt_drpen => drpEn,
501  gt_drpwe => drpWe,
502  gt_drpaddr => drpAddr,
503  gt_drpdi => drpDi,
504  core_to_gt_drprdy => drpRdy,
505  core_to_gt_drpdo => drpDo,
506  -- Transceiver Debug Interface
507  gt_txpcsreset => extRst,
508  gt_txpmareset => '0',
509  gt_rxpmareset => '0',
510  gt_txresetdone => open,
511  gt_rxresetdone => open,
512  gt_rxpmaresetdone => open,
513  gt_txbufstatus => open,
514  gt_rxbufstatus => open,
515  gt_rxrate => (others => '0'),
516  gt_eyescantrigger => '0',
517  gt_eyescanreset => '0',
518  gt_eyescandataerror => open,
519  gt_rxpolarity => gtRxPolarity,
520  gt_txpolarity => gtTxPolarity,
521  gt_rxdfelpmreset => '0',
522  gt_txprbsforceerr => '0',
523  gt_rxprbserr => open,
524  gt_rxcdrhold => '0',
525  gt_dmonitorout => open,
526  gt_rxlpmen => '0',
527  gt_txprecursor => gtTxPreCursor,
528  gt_txpostcursor => gtTxPostCursor,
529  gt_txdiffctrl => gtTxDiffCtrl,
530  gt_pcsrsvdin => (others => '0'),
531  gt_txoutclksel => "101");
532  end generate;
533 
534  -------------------------------------
535  -- 10GBASE-R's Reset Module
536  -------------------------------------
537  U_TenGigEthRst : entity work.TenGigEthGthUltraScaleRst
538  generic map (
539  TPD_G => TPD_G)
540  port map (
541  extRst => extRst,
542  coreClk => coreClk,
543  coreRst => coreRst,
544  phyClk => phyClock,
545  phyRst => phyReset,
546  txBufgGtRst => txBufgGtRst,
547  qplllock => status.qplllock,
548  txClk322 => txClk322,
549  txUsrClk => txUsrClk,
550  txUsrClk2 => txUsrClk2,
551  gtTxRst => status.gtTxRst,
552  gtRxRst => status.gtRxRst,
553  txUsrRdy => txUsrRdy,
554  rstCntDone => status.rstCntDone);
555 
556  -------------------------------
557  -- Configuration Vector Mapping
558  -------------------------------
559  configurationVector(0) <= config.pma_loopback;
560  configurationVector(15) <= config.pma_reset;
561  configurationVector(110) <= config.pcs_loopback;
562  configurationVector(111) <= config.pcs_reset;
563  configurationVector(399 downto 384) <= x"4C4B"; -- timer_ctrl = 0x4C4B (default)
564 
565  ----------------------
566  -- Core Status Mapping
567  ----------------------
568  status.phyReady <= status.core_status(0) or config.pcs_loopback;
569 
570  --------------------------------
571  -- Configuration/Status Register
572  --------------------------------
573  U_TenGigEthReg : entity work.TenGigEthReg
574  generic map (
575  TPD_G => TPD_G,
576  EN_AXI_REG_G => EN_AXI_REG_G,
577  AXI_ERROR_RESP_G => AXI_ERROR_RESP_G)
578  port map (
579  -- Local Configurations
580  localMac => localMac,
581  -- Clocks and resets
582  clk => phyClock,
583  rst => phyReset,
584  -- AXI-Lite Register Interface
585  axiReadMaster => mAxiReadMaster,
586  axiReadSlave => mAxiReadSlave,
587  axiWriteMaster => mAxiWriteMaster,
588  axiWriteSlave => mAxiWriteSlave,
589  -- Configuration and Status Interface
590  config => config,
591  status => status);
592 
593 end mapping;
TenGigEthReg.axiReadMaster
in axiReadMasterAxiLiteReadMasterType
Definition: TenGigEthReg.vhd:41
TenGigEthReg.EN_AXI_REG_G
EN_AXI_REG_Gboolean := false
Definition: TenGigEthReg.vhd:32
TenGigEthGthUltraScale.dmaObMaster
in dmaObMasterAxiStreamMasterType
Definition: TenGigEthGthUltraScale.vhd:46
EthMacTop.primClk
in primClksl
Definition: EthMacTop.vhd:65
EthMacTop.xgmiiTxd
out xgmiiTxdslv( 63 downto 0)
Definition: EthMacTop.vhd:93
TenGigEthGthUltraScale.dmaObSlave
out dmaObSlaveAxiStreamSlaveType
Definition: TenGigEthGthUltraScale.vhd:47
AxiLitePkg.AxiLiteWriteMasterType
AxiLiteWriteMasterType
Definition: AxiLitePkg.vhd:111
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
TenGigEthGthUltraScale.AXIS_CONFIG_G
AXIS_CONFIG_GAxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Definition: TenGigEthGthUltraScale.vhd:37
TenGigEthGthUltraScale.localMac
in localMacslv( 47 downto 0) := MAC_ADDR_INIT_C
Definition: TenGigEthGthUltraScale.vhd:40
EthMacTop.xgmiiRxc
in xgmiiRxcslv( 7 downto 0) :=( others => '0')
Definition: EthMacTop.vhd:92
AxiLiteAsync.mAxiReadMaster
out mAxiReadMasterAxiLiteReadMasterType
Definition: AxiLiteAsync.vhd:48
EthMacTop.ibMacPrimMaster
in ibMacPrimMasterAxiStreamMasterType
Definition: EthMacTop.vhd:67
TenGigEthReg.axiReadSlave
out axiReadSlaveAxiLiteReadSlaveType
Definition: TenGigEthReg.vhd:42
TenGigEthPkg.core_status
slv( 7 downto 0) core_status
Definition: TenGigEthPkg.vhd:62
EthMacTop.xgmiiTxc
out xgmiiTxcslv( 7 downto 0)
Definition: EthMacTop.vhd:94
AxiLiteAsync.mAxiWriteSlave
in mAxiWriteSlaveAxiLiteWriteSlaveType
Definition: AxiLiteAsync.vhd:51
TenGigEthGthUltraScale.axiLiteReadSlave
out axiLiteReadSlaveAxiLiteReadSlaveType
Definition: TenGigEthGthUltraScale.vhd:52
EthMacTop.obMacPrimSlave
in obMacPrimSlaveAxiStreamSlaveType
Definition: EthMacTop.vhd:70
TenGigEthReg.status
in statusTenGigEthStatus
Definition: TenGigEthReg.vhd:47
AxiLiteAsync.sAxiWriteSlave
out sAxiWriteSlaveAxiLiteWriteSlaveType
Definition: AxiLiteAsync.vhd:44
TenGigEthGthUltraScale.axiLiteWriteSlave
out axiLiteWriteSlaveAxiLiteWriteSlaveType
Definition: TenGigEthGthUltraScale.vhd:54
TenGigEthGthUltraScale.axiLiteReadMaster
in axiLiteReadMasterAxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Definition: TenGigEthGthUltraScale.vhd:51
AxiLiteAsync.sAxiReadMaster
in sAxiReadMasterAxiLiteReadMasterType
Definition: AxiLiteAsync.vhd:41
AxiLitePkg.AXI_RESP_SLVERR_C
slv( 1 downto 0) := "10" AXI_RESP_SLVERR_C
Definition: AxiLitePkg.vhd:36
AxiLiteAsync.sAxiWriteMaster
in sAxiWriteMasterAxiLiteWriteMasterType
Definition: AxiLiteAsync.vhd:43
EthMacTop.primRst
in primRstsl
Definition: EthMacTop.vhd:66
EthMacTop.obMacPrimMaster
out obMacPrimMasterAxiStreamMasterType
Definition: EthMacTop.vhd:69
EthMacTop.ethRst
in ethRstsl
Definition: EthMacTop.vhd:63
TenGigEthGthUltraScale.gtTxPreCursor
in gtTxPreCursorslv( 4 downto 0) := "00000"
Definition: TenGigEthGthUltraScale.vhd:66
EthMacTop.xgmiiRxd
in xgmiiRxdslv( 63 downto 0) :=( others => '0')
Definition: EthMacTop.vhd:91
TenGigEthGthUltraScale.mapping.configurationVector
slv( 535 downto 0) :=( others => '0') configurationVector
Definition: TenGigEthGthUltraScale.vhd:271
AxiLitePkg.AxiLiteReadMasterType
AxiLiteReadMasterType
Definition: AxiLitePkg.vhd:59
TenGigEthReg.axiWriteSlave
out axiWriteSlaveAxiLiteWriteSlaveType
Definition: TenGigEthReg.vhd:44
EthMacTop.ibMacPrimSlave
out ibMacPrimSlaveAxiStreamSlaveType
Definition: EthMacTop.vhd:68
EthMacTop.ethClk
in ethClksl
Definition: EthMacTop.vhd:62
TenGigEthGthUltraScale.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_SLVERR_C
Definition: TenGigEthGthUltraScale.vhd:35
TenGigEthGthUltraScale.dmaIbSlave
in dmaIbSlaveAxiStreamSlaveType
Definition: TenGigEthGthUltraScale.vhd:45
AxiLiteAsync.sAxiReadSlave
out sAxiReadSlaveAxiLiteReadSlaveType
Definition: AxiLiteAsync.vhd:42
TenGigEthReg.AXI_ERROR_RESP_G
AXI_ERROR_RESP_Gslv( 1 downto 0) := AXI_RESP_SLVERR_C
Definition: TenGigEthReg.vhd:33
EthMacTop.PRIM_CONFIG_G
PRIM_CONFIG_GAxiStreamConfigType := EMAC_AXIS_CONFIG_C
Definition: EthMacTop.vhd:49
TenGigEthReg.axiWriteMaster
in axiWriteMasterAxiLiteWriteMasterType
Definition: TenGigEthReg.vhd:43
EthMacTop.PHY_TYPE_G
PHY_TYPE_Gstring := "XGMII"
Definition: EthMacTop.vhd:36
AxiLitePkg.AXI_LITE_READ_MASTER_INIT_C
AxiLiteReadMasterType :=(araddr =>( others => '0'),arprot =>( others => '0'),arvalid => '0',rready => '1') AXI_LITE_READ_MASTER_INIT_C
Definition: AxiLitePkg.vhd:69
AxiStreamPkg.AXI_STREAM_CONFIG_INIT_C
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 16,TDEST_BITS_C => 4,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_NORMAL_C,TUSER_BITS_C => 4,TUSER_MODE_C => TUSER_NORMAL_C) AXI_STREAM_CONFIG_INIT_C
Definition: AxiStreamPkg.vhd:83
TenGigEthReg.config
out configTenGigEthConfig
Definition: TenGigEthReg.vhd:46
AxiLitePkg.AxiLiteReadSlaveType
AxiLiteReadSlaveType
Definition: AxiLitePkg.vhd:85
TenGigEthGthUltraScale.axiLiteWriteMaster
in axiLiteWriteMasterAxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Definition: TenGigEthGthUltraScale.vhd:53
TenGigEthReg.localMac
in localMacslv( 47 downto 0) := MAC_ADDR_INIT_C
Definition: TenGigEthReg.vhd:36
AxiLitePkg.AXI_LITE_WRITE_MASTER_INIT_C
AxiLiteWriteMasterType :=(awaddr =>( others => '0'),awprot =>( others => '0'),awvalid => '0',wdata =>( others => '0'),wstrb =>( others => '1'),wvalid => '0',bready => '1') AXI_LITE_WRITE_MASTER_INIT_C
Definition: AxiLitePkg.vhd:125
AxiLiteAsync.mAxiReadSlave
in mAxiReadSlaveAxiLiteReadSlaveType
Definition: AxiLiteAsync.vhd:49
AxiLiteAsync.mAxiClkRst
in mAxiClkRstsl
Definition: AxiLiteAsync.vhd:47
TenGigEthGthUltraScale.dmaIbMaster
out dmaIbMasterAxiStreamMasterType
Definition: TenGigEthGthUltraScale.vhd:44
EthMacTop.TPD_G
TPD_Gtime := 1 ns
Definition: EthMacTop.vhd:32
AxiLiteAsync.TPD_G
TPD_Gtime := 1 ns
Definition: AxiLiteAsync.vhd:32
EthMacTop.ethConfig
in ethConfigEthMacConfigType
Definition: EthMacTop.vhd:104
EthMacTop.ethStatus
out ethStatusEthMacStatusType
Definition: EthMacTop.vhd:105
TenGigEthGthUltraScale.gtTxPostCursor
in gtTxPostCursorslv( 4 downto 0) := "00000"
Definition: TenGigEthGthUltraScale.vhd:67
TenGigEthReg.TPD_G
TPD_Gtime := 1 ns
Definition: TenGigEthReg.vhd:31
AxiLiteAsync.mAxiWriteMaster
out mAxiWriteMasterAxiLiteWriteMasterType
Definition: AxiLiteAsync.vhd:50
AxiLiteAsync.sAxiClkRst
in sAxiClkRstsl
Definition: AxiLiteAsync.vhd:40
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
TenGigEthGthUltraScale.gtTxDiffCtrl
in gtTxDiffCtrlslv( 3 downto 0) := "1110"
Definition: TenGigEthGthUltraScale.vhd:68
EthMacTop.phyReady
in phyReadysl
Definition: EthMacTop.vhd:103