SURF  1.0
Generics | Ports | Libraries | Use Clauses
TenGigEthGthUltraScaleRst Entity Reference
ethernet » TenGigEthCore » gthUltraScale
+ Inheritance diagram for TenGigEthGthUltraScaleRst:
+ Collaboration diagram for TenGigEthGthUltraScaleRst:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns

Ports

extRst   in sl
coreClk   in sl
coreRst   out sl
phyClk   out sl
phyRst   out sl
txBufgGtRst   in sl
qplllock   in sl
txClk322   in sl
txUsrClk   out sl
txUsrClk2   out sl
gtTxRst   out sl
gtRxRst   out sl
txUsrRdy   out sl
rstCntDone   out sl

Detailed Description

See also
entity

Definition at line 30 of file TenGigEthGthUltraScaleRst.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file TenGigEthGthUltraScaleRst.vhd.

◆ extRst

extRst in sl
Port

Definition at line 34 of file TenGigEthGthUltraScaleRst.vhd.

◆ coreClk

coreClk in sl
Port

Definition at line 35 of file TenGigEthGthUltraScaleRst.vhd.

◆ coreRst

coreRst out sl
Port

Definition at line 36 of file TenGigEthGthUltraScaleRst.vhd.

◆ phyClk

phyClk out sl
Port

Definition at line 37 of file TenGigEthGthUltraScaleRst.vhd.

◆ phyRst

phyRst out sl
Port

Definition at line 38 of file TenGigEthGthUltraScaleRst.vhd.

◆ txBufgGtRst

txBufgGtRst in sl
Port

Definition at line 39 of file TenGigEthGthUltraScaleRst.vhd.

◆ qplllock

qplllock in sl
Port

Definition at line 40 of file TenGigEthGthUltraScaleRst.vhd.

◆ txClk322

txClk322 in sl
Port

Definition at line 41 of file TenGigEthGthUltraScaleRst.vhd.

◆ txUsrClk

txUsrClk out sl
Port

Definition at line 42 of file TenGigEthGthUltraScaleRst.vhd.

◆ txUsrClk2

txUsrClk2 out sl
Port

Definition at line 43 of file TenGigEthGthUltraScaleRst.vhd.

◆ gtTxRst

gtTxRst out sl
Port

Definition at line 44 of file TenGigEthGthUltraScaleRst.vhd.

◆ gtRxRst

gtRxRst out sl
Port

Definition at line 45 of file TenGigEthGthUltraScaleRst.vhd.

◆ txUsrRdy

txUsrRdy out sl
Port

Definition at line 46 of file TenGigEthGthUltraScaleRst.vhd.

◆ rstCntDone

rstCntDone out sl
Port

Definition at line 47 of file TenGigEthGthUltraScaleRst.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file TenGigEthGthUltraScaleRst.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file TenGigEthGthUltraScaleRst.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file TenGigEthGthUltraScaleRst.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file TenGigEthGthUltraScaleRst.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file TenGigEthGthUltraScaleRst.vhd.

◆ unisim

unisim
Library

Definition at line 25 of file TenGigEthGthUltraScaleRst.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 26 of file TenGigEthGthUltraScaleRst.vhd.

The documentation for this class was generated from the following file: