SURF  1.0
Components | Signals | Instantiations
mapping Architecture Reference

Components

TenGigEthGthUltraScale156p25MHzCore 
TenGigEthGthUltraScale312p5MHzCore 

Signals

mAxiReadMaster  AxiLiteReadMasterType
mAxiReadSlave  AxiLiteReadSlaveType
mAxiWriteMaster  AxiLiteWriteMasterType
mAxiWriteSlave  AxiLiteWriteSlaveType
phyRxd  slv ( 63 downto 0 )
phyRxc  slv ( 7 downto 0 )
phyTxd  slv ( 63 downto 0 )
phyTxc  slv ( 7 downto 0 )
areset  sl
coreRst  sl
phyClock  sl
phyReset  sl
txClk322  sl
txUsrClk  sl
txUsrClk2  sl
txUsrRdy  sl
txBufgGtRst  sl
drpReqGnt  sl
drpEn  sl
drpWe  sl
drpAddr  slv ( 15 downto 0 )
drpDi  slv ( 15 downto 0 )
drpRdy  sl
drpDo  slv ( 15 downto 0 )
configurationVector  slv ( 535 downto 0 ) := ( others = > ' 0 ' )
config  TenGigEthConfig
status  TenGigEthStatus
macRxAxisMaster  AxiStreamMasterType
macRxAxisCtrl  AxiStreamCtrlType
macTxAxisMaster  AxiStreamMasterType
macTxAxisSlave  AxiStreamSlaveType

Instantiations

u_axiliteasync  AxiLiteAsync <Entity AxiLiteAsync>
u_sync  SynchronizerVector <Entity SynchronizerVector>
u_mac  EthMacTop <Entity EthMacTop>
u_tengigethgthultrascalecore  tengigethgthultrascale156p25mhzcore
u_tengigethgthultrascalecore  tengigethgthultrascale312p5mhzcore
u_tengigethrst  TenGigEthGthUltraScaleRst <Entity TenGigEthGthUltraScaleRst>
u_tengigethreg  TenGigEthReg <Entity TenGigEthReg>

Detailed Description

Definition at line 83 of file TenGigEthGthUltraScale.vhd.

Member Data Documentation

◆ TenGigEthGthUltraScale156p25MHzCore

TenGigEthGthUltraScale156p25MHzCore
Component

Definition at line 85 of file TenGigEthGthUltraScale.vhd.

◆ TenGigEthGthUltraScale312p5MHzCore

TenGigEthGthUltraScale312p5MHzCore
Component

Definition at line 164 of file TenGigEthGthUltraScale.vhd.

◆ mAxiReadMaster

mAxiReadMaster AxiLiteReadMasterType
Signal

Definition at line 243 of file TenGigEthGthUltraScale.vhd.

◆ mAxiReadSlave

mAxiReadSlave AxiLiteReadSlaveType
Signal

Definition at line 244 of file TenGigEthGthUltraScale.vhd.

◆ mAxiWriteMaster

mAxiWriteMaster AxiLiteWriteMasterType
Signal

Definition at line 245 of file TenGigEthGthUltraScale.vhd.

◆ mAxiWriteSlave

mAxiWriteSlave AxiLiteWriteSlaveType
Signal

Definition at line 246 of file TenGigEthGthUltraScale.vhd.

◆ phyRxd

phyRxd slv ( 63 downto 0 )
Signal

Definition at line 248 of file TenGigEthGthUltraScale.vhd.

◆ phyRxc

phyRxc slv ( 7 downto 0 )
Signal

Definition at line 249 of file TenGigEthGthUltraScale.vhd.

◆ phyTxd

phyTxd slv ( 63 downto 0 )
Signal

Definition at line 250 of file TenGigEthGthUltraScale.vhd.

◆ phyTxc

phyTxc slv ( 7 downto 0 )
Signal

Definition at line 251 of file TenGigEthGthUltraScale.vhd.

◆ areset

areset sl
Signal

Definition at line 253 of file TenGigEthGthUltraScale.vhd.

◆ coreRst

coreRst sl
Signal

Definition at line 254 of file TenGigEthGthUltraScale.vhd.

◆ phyClock

phyClock sl
Signal

Definition at line 255 of file TenGigEthGthUltraScale.vhd.

◆ phyReset

phyReset sl
Signal

Definition at line 256 of file TenGigEthGthUltraScale.vhd.

◆ txClk322

txClk322 sl
Signal

Definition at line 257 of file TenGigEthGthUltraScale.vhd.

◆ txUsrClk

txUsrClk sl
Signal

Definition at line 258 of file TenGigEthGthUltraScale.vhd.

◆ txUsrClk2

txUsrClk2 sl
Signal

Definition at line 259 of file TenGigEthGthUltraScale.vhd.

◆ txUsrRdy

txUsrRdy sl
Signal

Definition at line 260 of file TenGigEthGthUltraScale.vhd.

◆ txBufgGtRst

txBufgGtRst sl
Signal

Definition at line 261 of file TenGigEthGthUltraScale.vhd.

◆ drpReqGnt

drpReqGnt sl
Signal

Definition at line 263 of file TenGigEthGthUltraScale.vhd.

◆ drpEn

drpEn sl
Signal

Definition at line 264 of file TenGigEthGthUltraScale.vhd.

◆ drpWe

drpWe sl
Signal

Definition at line 265 of file TenGigEthGthUltraScale.vhd.

◆ drpAddr

drpAddr slv ( 15 downto 0 )
Signal

Definition at line 266 of file TenGigEthGthUltraScale.vhd.

◆ drpDi

drpDi slv ( 15 downto 0 )
Signal

Definition at line 267 of file TenGigEthGthUltraScale.vhd.

◆ drpRdy

drpRdy sl
Signal

Definition at line 268 of file TenGigEthGthUltraScale.vhd.

◆ drpDo

drpDo slv ( 15 downto 0 )
Signal

Definition at line 269 of file TenGigEthGthUltraScale.vhd.

◆ configurationVector

configurationVector slv ( 535 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 271 of file TenGigEthGthUltraScale.vhd.

◆ config

config TenGigEthConfig
Signal

Definition at line 273 of file TenGigEthGthUltraScale.vhd.

◆ status

status TenGigEthStatus
Signal

Definition at line 274 of file TenGigEthGthUltraScale.vhd.

◆ macRxAxisMaster

macRxAxisMaster AxiStreamMasterType
Signal

Definition at line 276 of file TenGigEthGthUltraScale.vhd.

◆ macRxAxisCtrl

macRxAxisCtrl AxiStreamCtrlType
Signal

Definition at line 277 of file TenGigEthGthUltraScale.vhd.

◆ macTxAxisMaster

macTxAxisMaster AxiStreamMasterType
Signal

Definition at line 278 of file TenGigEthGthUltraScale.vhd.

◆ macTxAxisSlave

macTxAxisSlave AxiStreamSlaveType
Signal

Definition at line 279 of file TenGigEthGthUltraScale.vhd.

◆ u_axiliteasync

u_axiliteasync AxiLiteAsync
Instantiation

Definition at line 309 of file TenGigEthGthUltraScale.vhd.

◆ u_sync

u_sync SynchronizerVector
Instantiation

Definition at line 326 of file TenGigEthGthUltraScale.vhd.

◆ u_mac

u_mac EthMacTop
Instantiation

Definition at line 354 of file TenGigEthGthUltraScale.vhd.

◆ u_tengigethgthultrascalecore [1/2]

u_tengigethgthultrascalecore tengigethgthultrascale156p25mhzcore
Instantiation

Definition at line 445 of file TenGigEthGthUltraScale.vhd.

◆ u_tengigethgthultrascalecore [2/2]

u_tengigethgthultrascalecore tengigethgthultrascale312p5mhzcore
Instantiation

Definition at line 532 of file TenGigEthGthUltraScale.vhd.

◆ u_tengigethrst

u_tengigethrst TenGigEthGthUltraScaleRst
Instantiation

Definition at line 554 of file TenGigEthGthUltraScale.vhd.

◆ u_tengigethreg

u_tengigethreg TenGigEthReg
Instantiation

Definition at line 591 of file TenGigEthGthUltraScale.vhd.

The documentation for this class was generated from the following file: