SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteAsync Entity Reference
axi
+ Inheritance diagram for AxiLiteAsync:
+ Collaboration diagram for AxiLiteAsync:

Entities

STRUCTURE  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
COMMON_CLK_G  boolean := false
NUM_ADDR_BITS_G  natural := 32
PIPE_STAGES_G  integer range 0 to 16 := 0

Ports

sAxiClk   in sl
sAxiClkRst   in sl
sAxiReadMaster   in AxiLiteReadMasterType
sAxiReadSlave   out AxiLiteReadSlaveType
sAxiWriteMaster   in AxiLiteWriteMasterType
sAxiWriteSlave   out AxiLiteWriteSlaveType
mAxiClk   in sl
mAxiClkRst   in sl
mAxiReadMaster   out AxiLiteReadMasterType
mAxiReadSlave   in AxiLiteReadSlaveType
mAxiWriteMaster   out AxiLiteWriteMasterType
mAxiWriteSlave   in AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 30 of file AxiLiteAsync.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file AxiLiteAsync.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file AxiLiteAsync.vhd.

◆ COMMON_CLK_G

COMMON_CLK_G boolean := false
Generic

Definition at line 34 of file AxiLiteAsync.vhd.

◆ NUM_ADDR_BITS_G

NUM_ADDR_BITS_G natural := 32
Generic

Definition at line 35 of file AxiLiteAsync.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G integer range 0 to 16 := 0
Generic

Definition at line 36 of file AxiLiteAsync.vhd.

◆ sAxiClk

sAxiClk in sl
Port

Definition at line 39 of file AxiLiteAsync.vhd.

◆ sAxiClkRst

sAxiClkRst in sl
Port

Definition at line 40 of file AxiLiteAsync.vhd.

◆ sAxiReadMaster

sAxiReadMaster in AxiLiteReadMasterType
Port

Definition at line 41 of file AxiLiteAsync.vhd.

◆ sAxiReadSlave

sAxiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 42 of file AxiLiteAsync.vhd.

◆ sAxiWriteMaster

sAxiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 43 of file AxiLiteAsync.vhd.

◆ sAxiWriteSlave

sAxiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 44 of file AxiLiteAsync.vhd.

◆ mAxiClk

mAxiClk in sl
Port

Definition at line 46 of file AxiLiteAsync.vhd.

◆ mAxiClkRst

mAxiClkRst in sl
Port

Definition at line 47 of file AxiLiteAsync.vhd.

◆ mAxiReadMaster

mAxiReadMaster out AxiLiteReadMasterType
Port

Definition at line 48 of file AxiLiteAsync.vhd.

◆ mAxiReadSlave

mAxiReadSlave in AxiLiteReadSlaveType
Port

Definition at line 49 of file AxiLiteAsync.vhd.

◆ mAxiWriteMaster

mAxiWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 50 of file AxiLiteAsync.vhd.

◆ mAxiWriteSlave

mAxiWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 51 of file AxiLiteAsync.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiLiteAsync.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiLiteAsync.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file AxiLiteAsync.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 23 of file AxiLiteAsync.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 25 of file AxiLiteAsync.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file AxiLiteAsync.vhd.

The documentation for this class was generated from the following file: