SURF
1.0
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Entities | |
rtl | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
std_logic_unsigned | |
std_logic_arith | |
StdRtlPkg | Package <StdRtlPkg> |
AxiLitePkg | Package <AxiLitePkg> |
TenGigEthPkg | Package <TenGigEthPkg> |
Generics | |
TPD_G | time := 1 ns |
EN_AXI_REG_G | boolean := false |
AXI_ERROR_RESP_G | slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C |
Ports | |
localMac | in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C |
clk | in sl |
rst | in sl |
axiReadMaster | in AxiLiteReadMasterType |
axiReadSlave | out AxiLiteReadSlaveType |
axiWriteMaster | in AxiLiteWriteMasterType |
axiWriteSlave | out AxiLiteWriteSlaveType |
config | out TenGigEthConfig |
status | in TenGigEthStatus |
Definition at line 29 of file TenGigEthReg.vhd.
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Generic |
Definition at line 31 of file TenGigEthReg.vhd.
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Generic |
Definition at line 32 of file TenGigEthReg.vhd.
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Generic |
Definition at line 33 of file TenGigEthReg.vhd.
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Port |
Definition at line 36 of file TenGigEthReg.vhd.
Definition at line 38 of file TenGigEthReg.vhd.
Definition at line 39 of file TenGigEthReg.vhd.
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Port |
Definition at line 41 of file TenGigEthReg.vhd.
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Port |
Definition at line 42 of file TenGigEthReg.vhd.
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Port |
Definition at line 43 of file TenGigEthReg.vhd.
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Port |
Definition at line 44 of file TenGigEthReg.vhd.
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Port |
Definition at line 46 of file TenGigEthReg.vhd.
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Port |
Definition at line 47 of file TenGigEthReg.vhd.
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Library |
Definition at line 18 of file TenGigEthReg.vhd.
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Package |
Definition at line 19 of file TenGigEthReg.vhd.
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Package |
Definition at line 20 of file TenGigEthReg.vhd.
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Package |
Definition at line 21 of file TenGigEthReg.vhd.
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Package |
Definition at line 23 of file TenGigEthReg.vhd.
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Package |
Definition at line 24 of file TenGigEthReg.vhd.
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Package |
Definition at line 25 of file TenGigEthReg.vhd.