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TenGigEthGthUltraScale Entity Reference
ethernet » TenGigEthCore » gthUltraScale
+ Inheritance diagram for TenGigEthGthUltraScale:
+ Collaboration diagram for TenGigEthGthUltraScale:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
TenGigEthPkg  Package <TenGigEthPkg>
EthMacPkg  Package <EthMacPkg>

Generics

TPD_G  time := 1 ns
REF_CLK_FREQ_G  real := 156 . 25E + 6
EN_AXI_REG_G  boolean := false
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

localMac   in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk   in sl
dmaRst   in sl
dmaIbMaster   out AxiStreamMasterType
dmaIbSlave   in AxiStreamSlaveType
dmaObMaster   in AxiStreamMasterType
dmaObSlave   out AxiStreamSlaveType
axiLiteClk   in sl := ' 0 '
axiLiteRst   in sl := ' 0 '
axiLiteReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave   out AxiLiteReadSlaveType
axiLiteWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave   out AxiLiteWriteSlaveType
sigDet   in sl := ' 1 '
txFault   in sl := ' 0 '
txDisable   out sl
extRst   in sl
coreClk   in sl
phyClk   out sl
phyRst   out sl
phyReady   out sl
gtTxPreCursor   in slv ( 4 downto 0 ) := " 00000 "
gtTxPostCursor   in slv ( 4 downto 0 ) := " 00000 "
gtTxDiffCtrl   in slv ( 3 downto 0 ) := " 1110 "
gtRxPolarity   in sl := ' 0 '
gtTxPolarity   in sl := ' 0 '
qplllock   in sl
qplloutclk   in sl
qplloutrefclk   in sl
qpllRst   out sl
gtTxP   out sl
gtTxN   out sl
gtRxP   in sl
gtRxN   in sl

Detailed Description

See also
entity

Definition at line 29 of file TenGigEthGthUltraScale.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file TenGigEthGthUltraScale.vhd.

◆ REF_CLK_FREQ_G

REF_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 32 of file TenGigEthGthUltraScale.vhd.

◆ EN_AXI_REG_G

EN_AXI_REG_G boolean := false
Generic

Definition at line 34 of file TenGigEthGthUltraScale.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 35 of file TenGigEthGthUltraScale.vhd.

◆ AXIS_CONFIG_G

AXIS_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 37 of file TenGigEthGthUltraScale.vhd.

◆ localMac

localMac in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
Port

Definition at line 40 of file TenGigEthGthUltraScale.vhd.

◆ dmaClk

dmaClk in sl
Port

Definition at line 42 of file TenGigEthGthUltraScale.vhd.

◆ dmaRst

dmaRst in sl
Port

Definition at line 43 of file TenGigEthGthUltraScale.vhd.

◆ dmaIbMaster

dmaIbMaster out AxiStreamMasterType
Port

Definition at line 44 of file TenGigEthGthUltraScale.vhd.

◆ dmaIbSlave

dmaIbSlave in AxiStreamSlaveType
Port

Definition at line 45 of file TenGigEthGthUltraScale.vhd.

◆ dmaObMaster

dmaObMaster in AxiStreamMasterType
Port

Definition at line 46 of file TenGigEthGthUltraScale.vhd.

◆ dmaObSlave

dmaObSlave out AxiStreamSlaveType
Port

Definition at line 47 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteClk

axiLiteClk in sl := ' 0 '
Port

Definition at line 49 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteRst

axiLiteRst in sl := ' 0 '
Port

Definition at line 50 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteReadMaster

axiLiteReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 51 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteReadSlave

axiLiteReadSlave out AxiLiteReadSlaveType
Port

Definition at line 52 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteWriteMaster

axiLiteWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 53 of file TenGigEthGthUltraScale.vhd.

◆ axiLiteWriteSlave

axiLiteWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 54 of file TenGigEthGthUltraScale.vhd.

◆ sigDet

sigDet in sl := ' 1 '
Port

Definition at line 56 of file TenGigEthGthUltraScale.vhd.

◆ txFault

txFault in sl := ' 0 '
Port

Definition at line 57 of file TenGigEthGthUltraScale.vhd.

◆ txDisable

txDisable out sl
Port

Definition at line 58 of file TenGigEthGthUltraScale.vhd.

◆ extRst

extRst in sl
Port

Definition at line 60 of file TenGigEthGthUltraScale.vhd.

◆ coreClk

coreClk in sl
Port

Definition at line 61 of file TenGigEthGthUltraScale.vhd.

◆ phyClk

phyClk out sl
Port

Definition at line 62 of file TenGigEthGthUltraScale.vhd.

◆ phyRst

phyRst out sl
Port

Definition at line 63 of file TenGigEthGthUltraScale.vhd.

◆ phyReady

phyReady out sl
Port

Definition at line 64 of file TenGigEthGthUltraScale.vhd.

◆ gtTxPreCursor

gtTxPreCursor in slv ( 4 downto 0 ) := " 00000 "
Port

Definition at line 66 of file TenGigEthGthUltraScale.vhd.

◆ gtTxPostCursor

gtTxPostCursor in slv ( 4 downto 0 ) := " 00000 "
Port

Definition at line 67 of file TenGigEthGthUltraScale.vhd.

◆ gtTxDiffCtrl

gtTxDiffCtrl in slv ( 3 downto 0 ) := " 1110 "
Port

Definition at line 68 of file TenGigEthGthUltraScale.vhd.

◆ gtRxPolarity

gtRxPolarity in sl := ' 0 '
Port

Definition at line 69 of file TenGigEthGthUltraScale.vhd.

◆ gtTxPolarity

gtTxPolarity in sl := ' 0 '
Port

Definition at line 70 of file TenGigEthGthUltraScale.vhd.

◆ qplllock

qplllock in sl
Port

Definition at line 72 of file TenGigEthGthUltraScale.vhd.

◆ qplloutclk

qplloutclk in sl
Port

Definition at line 73 of file TenGigEthGthUltraScale.vhd.

◆ qplloutrefclk

qplloutrefclk in sl
Port

Definition at line 74 of file TenGigEthGthUltraScale.vhd.

◆ qpllRst

qpllRst out sl
Port

Definition at line 75 of file TenGigEthGthUltraScale.vhd.

◆ gtTxP

gtTxP out sl
Port

Definition at line 77 of file TenGigEthGthUltraScale.vhd.

◆ gtTxN

gtTxN out sl
Port

Definition at line 78 of file TenGigEthGthUltraScale.vhd.

◆ gtRxP

gtRxP in sl
Port

Definition at line 79 of file TenGigEthGthUltraScale.vhd.

◆ gtRxN

gtRxN in sl
Port

Definition at line 80 of file TenGigEthGthUltraScale.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file TenGigEthGthUltraScale.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file TenGigEthGthUltraScale.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file TenGigEthGthUltraScale.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 22 of file TenGigEthGthUltraScale.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file TenGigEthGthUltraScale.vhd.

◆ TenGigEthPkg

TenGigEthPkg
Package

Definition at line 24 of file TenGigEthGthUltraScale.vhd.

◆ EthMacPkg

EthMacPkg
Package

Definition at line 25 of file TenGigEthGthUltraScale.vhd.

The documentation for this class was generated from the following file: