SURF  1.0
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TenGigEthGth7Wrapper Entity Reference
ethernet » TenGigEthCore » gth7
+ Inheritance diagram for TenGigEthGth7Wrapper:
+ Collaboration diagram for TenGigEthGth7Wrapper:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
TenGigEthPkg  Package <TenGigEthPkg>

Generics

TPD_G  time := 1 ns
NUM_LANE_G  natural range 1 to 4 := 1
USE_GTREFCLK_G  boolean := false
REFCLK_DIV2_G  boolean := false
QPLL_REFCLK_SEL_G  bit_vector := " 001 "
EN_AXI_REG_G  boolean := false
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
AXIS_CONFIG_G  AxiStreamConfigArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CONFIG_INIT_C )

Ports

localMac   in Slv48Array ( NUM_LANE_G - 1 downto 0 ) := ( others = > MAC_ADDR_INIT_C )
dmaClk   in slv ( NUM_LANE_G - 1 downto 0 )
dmaRst   in slv ( NUM_LANE_G - 1 downto 0 )
dmaIbMasters   out AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
dmaIbSlaves   in AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
dmaObMasters   in AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
dmaObSlaves   out AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
axiLiteClk   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteRst   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteReadMasters   in AxiLiteReadMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axiLiteReadSlaves   out AxiLiteReadSlaveArray ( NUM_LANE_G - 1 downto 0 )
axiLiteWriteMasters   in AxiLiteWriteMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axiLiteWriteSlaves   out AxiLiteWriteSlaveArray ( NUM_LANE_G - 1 downto 0 )
sigDet   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 1 ' )
txFault   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
txDisable   out slv ( NUM_LANE_G - 1 downto 0 )
extRst   in sl := ' 0 '
phyClk   out sl
phyRst   out sl
phyReady   out slv ( NUM_LANE_G - 1 downto 0 )
gtRefClk   in sl := ' 0 '
gtClkP   in sl := ' 1 '
gtClkN   in sl := ' 0 '
gtTxP   out slv ( NUM_LANE_G - 1 downto 0 )
gtTxN   out slv ( NUM_LANE_G - 1 downto 0 )
gtRxP   in slv ( NUM_LANE_G - 1 downto 0 )
gtRxN   in slv ( NUM_LANE_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 29 of file TenGigEthGth7Wrapper.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file TenGigEthGth7Wrapper.vhd.

◆ NUM_LANE_G

NUM_LANE_G natural range 1 to 4 := 1
Generic

Definition at line 32 of file TenGigEthGth7Wrapper.vhd.

◆ USE_GTREFCLK_G

USE_GTREFCLK_G boolean := false
Generic

Definition at line 34 of file TenGigEthGth7Wrapper.vhd.

◆ REFCLK_DIV2_G

REFCLK_DIV2_G boolean := false
Generic

Definition at line 35 of file TenGigEthGth7Wrapper.vhd.

◆ QPLL_REFCLK_SEL_G

QPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 36 of file TenGigEthGth7Wrapper.vhd.

◆ EN_AXI_REG_G

EN_AXI_REG_G boolean := false
Generic

Definition at line 38 of file TenGigEthGth7Wrapper.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 39 of file TenGigEthGth7Wrapper.vhd.

◆ AXIS_CONFIG_G

AXIS_CONFIG_G AxiStreamConfigArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CONFIG_INIT_C )
Generic

Definition at line 41 of file TenGigEthGth7Wrapper.vhd.

◆ localMac

localMac in Slv48Array ( NUM_LANE_G - 1 downto 0 ) := ( others = > MAC_ADDR_INIT_C )
Port

Definition at line 44 of file TenGigEthGth7Wrapper.vhd.

◆ dmaClk

dmaClk in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 46 of file TenGigEthGth7Wrapper.vhd.

◆ dmaRst

dmaRst in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 47 of file TenGigEthGth7Wrapper.vhd.

◆ dmaIbMasters

dmaIbMasters out AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 48 of file TenGigEthGth7Wrapper.vhd.

◆ dmaIbSlaves

dmaIbSlaves in AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 49 of file TenGigEthGth7Wrapper.vhd.

◆ dmaObMasters

dmaObMasters in AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 50 of file TenGigEthGth7Wrapper.vhd.

◆ dmaObSlaves

dmaObSlaves out AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 51 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteClk

axiLiteClk in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 53 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteRst

axiLiteRst in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 54 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteReadMasters

axiLiteReadMasters in AxiLiteReadMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
Port

Definition at line 55 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteReadSlaves

axiLiteReadSlaves out AxiLiteReadSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 56 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteWriteMasters

axiLiteWriteMasters in AxiLiteWriteMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
Port

Definition at line 57 of file TenGigEthGth7Wrapper.vhd.

◆ axiLiteWriteSlaves

axiLiteWriteSlaves out AxiLiteWriteSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 58 of file TenGigEthGth7Wrapper.vhd.

◆ sigDet

sigDet in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 1 ' )
Port

Definition at line 60 of file TenGigEthGth7Wrapper.vhd.

◆ txFault

txFault in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 61 of file TenGigEthGth7Wrapper.vhd.

◆ txDisable

txDisable out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 62 of file TenGigEthGth7Wrapper.vhd.

◆ extRst

extRst in sl := ' 0 '
Port

Definition at line 64 of file TenGigEthGth7Wrapper.vhd.

◆ phyClk

phyClk out sl
Port

Definition at line 65 of file TenGigEthGth7Wrapper.vhd.

◆ phyRst

phyRst out sl
Port

Definition at line 66 of file TenGigEthGth7Wrapper.vhd.

◆ phyReady

phyReady out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 67 of file TenGigEthGth7Wrapper.vhd.

◆ gtRefClk

gtRefClk in sl := ' 0 '
Port

Definition at line 69 of file TenGigEthGth7Wrapper.vhd.

◆ gtClkP

gtClkP in sl := ' 1 '
Port

Definition at line 70 of file TenGigEthGth7Wrapper.vhd.

◆ gtClkN

gtClkN in sl := ' 0 '
Port

Definition at line 71 of file TenGigEthGth7Wrapper.vhd.

◆ gtTxP

gtTxP out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 73 of file TenGigEthGth7Wrapper.vhd.

◆ gtTxN

gtTxN out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 74 of file TenGigEthGth7Wrapper.vhd.

◆ gtRxP

gtRxP in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 75 of file TenGigEthGth7Wrapper.vhd.

◆ gtRxN

gtRxN in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 76 of file TenGigEthGth7Wrapper.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file TenGigEthGth7Wrapper.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file TenGigEthGth7Wrapper.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file TenGigEthGth7Wrapper.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 23 of file TenGigEthGth7Wrapper.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file TenGigEthGth7Wrapper.vhd.

◆ TenGigEthPkg

TenGigEthPkg
Package

Definition at line 25 of file TenGigEthGth7Wrapper.vhd.

The documentation for this class was generated from the following file: