TenGigEthGthUltraScale.mapping Architecture Reference

Architecture >> TenGigEthGthUltraScale::mapping

Processes
PROCESS_228	( phyClock )

Components
TenGigEthGthUltraScale156p25MHzCore

Signals
mAxiReadMaster	AxiLiteReadMasterType
mAxiReadSlave	AxiLiteReadSlaveType
mAxiWriteMaster	AxiLiteWriteMasterType
mAxiWriteSlave	AxiLiteWriteSlaveType
phyRxd	slv ( 63 downto 0 )
phyRxc	slv ( 7 downto 0 )
phyTxd	slv ( 63 downto 0 )
phyTxc	slv ( 7 downto 0 )
txGtClk	sl
phyClock	sl
phyReset	sl
config	TenGigEthConfig
status	TenGigEthStatus
macRxAxisMaster	AxiStreamMasterType
macRxAxisCtrl	AxiStreamCtrlType
macTxAxisMaster	AxiStreamMasterType
macTxAxisSlave	AxiStreamSlaveType
xgmiiRxd	slv ( 63 downto 0 )
xgmiiRxc	slv ( 7 downto 0 )
xgmiiTxd	slv ( 63 downto 0 )
xgmiiTxc	slv ( 7 downto 0 )
areset	sl
coreRst	sl
txClk322	sl
txUsrClk	sl
txUsrClk2	sl
txUsrRdy	sl
txBufgGtRst	sl
drpReqGnt	sl
drpEn	sl
drpWe	sl
drpAddr	slv ( 15 downto 0 )
drpDi	slv ( 15 downto 0 )
drpRdy	sl
drpDo	slv ( 15 downto 0 )
configurationVector	slv ( 535 downto 0 ) := ( others = > ' 0 ' )
statusReg	TenGigEthStatus

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_mac	EthMacTop <Entity EthMacTop>
u_tengigethgthultrascalecore	tengigethgthultrascale156p25mhzcore
u_tengigethrst	TenGigEthGthUltraScaleRst <Entity TenGigEthGthUltraScaleRst>
u_tengigethreg	TenGigEthReg <Entity TenGigEthReg>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_sync	SynchronizerVector <Entity SynchronizerVector>
u_mac	EthMacTop <Entity EthMacTop>
u_tengigethgthultrascalecore	tengigethgthultrascale156p25mhzcore
u_tengigethrst	TenGigEthGthUltraScaleRst <Entity TenGigEthGthUltraScaleRst>
u_tengigethreg	TenGigEthReg <Entity TenGigEthReg>

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The documentation for this design unit was generated from the following files:

• ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd
• ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd