Inheritance diagram for TenGigEthGthUltraScale:

Collaboration diagram for TenGigEthGthUltraScale:

Entities
TenGigEthGthUltraScale.mapping	architecture

Generics
TPD_G	time := 1 ns
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
EN_AXI_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axiLiteClk	in	sl := ' 0 '
axiLiteRst	in	sl := ' 0 '
axiLiteReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave	out	AxiLiteReadSlaveType
axiLiteWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave	out	AxiLiteWriteSlaveType
coreClk	in	sl
coreRst	in	sl
phyClk	out	sl
phyRst	out	sl
phyReady	out	sl
gtTxPreCursor	in	slv ( 4 downto 0 ) := " 00000 "
gtTxPostCursor	in	slv ( 4 downto 0 ) := " 00000 "
gtTxDiffCtrl	in	slv ( 4 downto 0 ) := " 11100 "
gtRxPolarity	in	sl := ' 0 '
gtTxPolarity	in	sl := ' 0 '
qplllock	in	slv ( 1 downto 0 )
qplloutclk	in	slv ( 1 downto 0 )
qplloutrefclk	in	slv ( 1 downto 0 )
qpllRst	out	slv ( 1 downto 0 )
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
sigDet	in	sl := ' 1 '
txFault	in	sl := ' 0 '
txDisable	out	sl
extRst	in	sl

The documentation for this design unit was generated from the following files:

Entities

Libraries