TenGigEthReg Entity Reference

Inheritance diagram for TenGigEthReg:

Collaboration diagram for TenGigEthReg:

Entities
TenGigEthReg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
TenGigEthPkg	Package <TenGigEthPkg>

Generics
TPD_G	time := 1 ns
EN_AXI_REG_G	boolean := false

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
clk	in	sl
rst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
config	out	TenGigEthConfig
status	in	TenGigEthStatus

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd