Inheritance diagram for EthMacTop:

Collaboration diagram for EthMacTop:

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
PAUSE_EN_G	boolean := true
PAUSE_512BITS_G	positive range 1 to 1024 := 8
PHY_TYPE_G	string := " XGMII "
DROP_ERR_PKT_G	boolean := true
JUMBO_G	boolean := true
INT_PIPE_STAGES_G	natural := 1
PIPE_STAGES_G	natural := 1
FIFO_ADDR_WIDTH_G	positive := 11
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
ROCEV2_EN_G	boolean := false
FILT_EN_G	boolean := false
PRIM_COMMON_CLK_G	boolean := false
PRIM_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C
BYP_EN_G	boolean := false
BYP_ETH_TYPE_G	slv ( 15 downto 0 ) := x " 0000 "
BYP_COMMON_CLK_G	boolean := false
BYP_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
ethClkEn	in	sl := ' 1 '
ethClk	in	sl
ethRst	in	sl
primClk	in	sl
primRst	in	sl
ibMacPrimMaster	in	AxiStreamMasterType
ibMacPrimSlave	out	AxiStreamSlaveType
obMacPrimMaster	out	AxiStreamMasterType
obMacPrimSlave	in	AxiStreamSlaveType
bypClk	in	sl := ' 0 '
bypRst	in	sl := ' 0 '
ibMacBypMaster	in	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
ibMacBypSlave	out	AxiStreamSlaveType
obMacBypMaster	out	AxiStreamMasterType
obMacBypSlave	in	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
xlgmiiRxd	in	slv ( 127 downto 0 ) := ( others = > ' 0 ' )
xlgmiiRxc	in	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
xlgmiiTxd	out	slv ( 127 downto 0 )
xlgmiiTxc	out	slv ( 15 downto 0 )
xgmiiRxd	in	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
xgmiiRxc	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
xgmiiTxd	out	slv ( 63 downto 0 )
xgmiiTxc	out	slv ( 7 downto 0 )
gmiiRxDv	in	sl := ' 0 '
gmiiRxEr	in	sl := ' 0 '
gmiiRxd	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
gmiiTxEn	out	sl
gmiiTxEr	out	sl
gmiiTxd	out	slv ( 7 downto 0 )
phyReady	in	sl
ethConfig	in	EthMacConfigType
ethStatus	out	EthMacStatusType

The documentation for this design unit was generated from the following file:

Entities

Libraries