Architecture >> SugoiSubordinateSimModel::mapping

Constants
GET_BUILD_INFO_C	BuildInfoRetType := toBuildInfo ( BUILD_INFO_C )
MOD_BUILD_INFO_C	BuildInfoRetType := ( buildString = > GET_BUILD_INFO_C.buildString , fwVersion = > GET_BUILD_INFO_C.fwVersion , gitHash = > x " 1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA " )
SIM_BUILD_INFO_C	slv ( 2239 downto 0 ) := toSlv ( MOD_BUILD_INFO_C )
VERSION_INDEX_C	natural := 0
BROKEN_INDEX_C	natural := 1
NUM_AXIL_MASTERS_C	natural := 2
AXIL_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , x " 0000_0000 " , NUM_ADDR_BITS_G , NUM_ADDR_BITS_G- 1 )

Signals
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_INIT_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_OK_C )
clk	sl
rx	sl
tx	sl
reset	sl

Instantiations
u_clk_in	ibufds
u_rx	ibufds
u_core	SugoiSubordinateCore <Entity SugoiSubordinateCore>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_version	AxiVersion <Entity AxiVersion>
u_tx	OutputBufferReg <Entity OutputBufferReg>
u_clk_out	ClkOutBufDiff <Entity ClkOutBufDiff>

The documentation for this design unit was generated from the following file:

Constants

Signals