AxiVersion Entity Reference

Inheritance diagram for AxiVersion:

Collaboration diagram for AxiVersion:

Entities
AxiVersion.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
BUILD_INFO_G	BuildInfoType
SIM_DNA_VALUE_G	slv := X " 000000000000000000000000 "
DEVICE_ID_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
CLK_PERIOD_G	real := 8 . 0E - 9
XIL_DEVICE_G	string := " 7SERIES "
EN_DEVICE_DNA_G	boolean := false
EN_DS2411_G	boolean := false
EN_ICAP_G	boolean := false
USE_SLOWCLK_G	boolean := false
BUFR_CLK_DIV_G	positive := 8
AUTO_RELOAD_EN_G	boolean := false
AUTO_RELOAD_TIME_G	positive := 10
AUTO_RELOAD_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
userReset	out	sl
fpgaEnReload	in	sl := ' 1 '
fpgaReload	out	sl
fpgaReloadAddr	out	slv ( 31 downto 0 )
upTimeCnt	out	slv ( 31 downto 0 )
slowClk	in	sl := ' 0 '
dnaValueOut	out	slv ( 127 downto 0 )
fdValueOut	out	slv ( 63 downto 0 )
userValues	in	Slv32Array ( 0 to 63 ) := ( others = > X " 00000000 " )
fdSerSdio	inout	sl := ' Z '

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiVersion.vhd
• build/SRC_VHDL/surf/AxiVersion.vhd