AxiVersion.rtl Architecture Reference

Architecture >> AxiVersion::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , dnaValue , fdValue , fpgaEnReload , r , userValues )
seq	( axiClk , axiRst )
comb	( axiReadMaster , axiRst , axiWriteMaster , dnaValue , fdValue , fpgaEnReload , r , userValues )
seq	( axiClk , axiRst )

Constants
TIMEOUT_1HZ_C	natural := ( getTimeRatio ( 1 . 0 , CLK_PERIOD_G ) - 1 )
COUNTER_ZERO_C	slv ( 31 downto 0 ) := X " 00000000 "
BUILD_INFO_C	BuildInfoRetType := toBuildInfo ( BUILD_INFO_G )
BUILD_STRING_ROM_C	Slv32Array ( 0 to 63 ) := BUILD_INFO_C.buildString
REG_INIT_C	RegType := ( upTimeCnt = > ( others = > ' 0 ' ) , timer = > 0 , scratchPad = > ( others = > ' 0 ' ) , reloadTimer = > 0 , userReset = > ' 0 ' , fpgaReload = > ' 0 ' , haltReload = > ' 0 ' , fpgaReloadAddr = > AUTO_RELOAD_ADDR_G , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
dnaValue	slv ( 127 downto 0 ) := ( others = > ' 0 ' )
fdValue	slv ( 63 downto 0 ) := ( others = > ' 0 ' )

Attributes
rom_style	string
rom_style	constant is " distributed "
rom_extract	string
rom_extract	constant is " TRUE "
syn_keep	string
syn_keep	constant is " TRUE "

Records
RegType

Instantiations
devicedna_1	DeviceDna <Entity DeviceDna>
ds2411core_1	DS2411Core <Entity DS2411Core>
iprog_1	Iprog <Entity Iprog>
devicedna_1	DeviceDna <Entity DeviceDna>
ds2411core_1	DS2411Core <Entity DS2411Core>
iprog_1	Iprog <Entity Iprog>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiVersion.vhd
• build/SRC_VHDL/surf/AxiVersion.vhd