DeviceDna Entity Reference

Inheritance diagram for DeviceDna:

Collaboration diagram for DeviceDna:

Entities
DeviceDna.mapping	architecture
DeviceDna.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
TextUtilPkg	Package <TextUtilPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
XIL_DEVICE_G	string := " 7SERIES "
USE_SLOWCLK_G	boolean := false
BUFR_CLK_DIV_G	positive := 8
SIM_DNA_VALUE_G	slv := X " 000000000000000000000000 "

Ports
clk	in	sl
rst	in	sl
slowClk	in	sl := ' 0 '
dnaValue	out	slv ( 127 downto 0 ) := ( others = > ' 0 ' )
dnaValid	out	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/DeviceDnaDummy.vhd
• xilinx/dummy/DeviceDnaDummy.vhd
• xilinx/general/rtl/DeviceDna.vhd