Iprog Entity Reference

Inheritance diagram for Iprog:

Collaboration diagram for Iprog:

Entities
Iprog.mapping	architecture
Iprog.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
TextUtilPkg	Package <TextUtilPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
XIL_DEVICE_G	string := " 7SERIES "
USE_SLOWCLK_G	boolean := false
BUFR_CLK_DIV_G	positive := 8

Ports
clk	in	sl := ' 0 '
rst	in	sl := ' 0 '
slowClk	in	sl := ' 0 '
start	in	sl := ' 0 '
bootAddress	in	slv ( 31 downto 0 ) := X " 00000000 "

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/IprogDummy.vhd
• xilinx/dummy/IprogDummy.vhd
• xilinx/general/rtl/Iprog.vhd