DS2411Core Entity Reference

Inheritance diagram for DS2411Core:

Collaboration diagram for DS2411Core:

Entities
DS2411Core.mapping	architecture
DS2411Core.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
std_logic_arith
std_logic_unsigned
vcomponents

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SIMULATION_G	boolean := false
SIM_OUTPUT_G	slv ( 63 downto 0 ) := x " 0123456789ABCDEF "
CLK_PERIOD_G	real := 6 . 4E - 9
SMPL_TIME_G	real := 13 . 1E - 6

Ports
clk	in	sl := ' 0 '
rst	in	sl := ' 0 '
fdSerSdio	inout	sl
fdSerDin	out	sl := ' 0 '
fdValue	out	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
fdValid	out	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/DS2411CoreDummy.vhd
• devices/Maxim/dummy/DS2411CoreDummy.vhd
• devices/Maxim/rtl/DS2411Core.vhd