DS2411Core.rtl Architecture Reference

Architecture >> DS2411Core::rtl

Processes
PROCESS_201	( clk , rst )
PROCESS_202	( bitCnt , curState , timeCnt )

Types
StateType	( ST_START , ST_RESET , ST_WAIT , ST_WRITE , ST_PAUSE , ST_READ , ST_DONE )

Signals
curState	StateType := ST_START
nxtState	StateType := ST_START
setOutLow	sl := ' 0 '
fdValidSet	sl := ' 0 '
iFdSerDin	sl := ' 0 '
bitSet	sl := ' 0 '
bitCntEn	sl := ' 0 '
bitCntRst	sl := ' 1 '
timeCntRst	sl := ' 1 '
timeCnt	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
bitCnt	slv ( 5 downto 0 ) := ( others = > ' 0 ' )
setOutLowInv	sl
fdSerial	slv ( 63 downto 0 ) := ( others = > ' 0 ' )

Instantiations
fd_ser_sdio_buft	IoBufWrapper <Entity IoBufWrapper>

---

The documentation for this design unit was generated from the following file:

• devices/Maxim/rtl/DS2411Core.vhd