SaltRxLvds.rtl Architecture Reference

Architecture >> SaltRxLvds::rtl

Processes
comb	( data , dataK , linkUp , r , rst125MHz )
seq	( clk125MHz )

Constants
REG_INIT_C	RegType := ( rxEn = > ' 0 ' , rxErr = > ' 0 ' , rxData = > ( others = > ' 0 ' ) , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
dlyLoad	sl
dlyCfg	slv ( 8 downto 0 )
data8b	slv ( 7 downto 0 )
data10b	slv ( 9 downto 0 )
data	slv ( 7 downto 0 )
dataK	sl
codeError	sl
dispError	sl
slip	sl
linkUp	sl
enUsrDlyCfgSync	sl
usrDlyCfgSync	slv ( 8 downto 0 )
bypFirstBerDetSync	sl
minEyeWidthSync	slv ( 7 downto 0 )
lockingCntCfgSync	slv ( 23 downto 0 )

Records
RegType

Instantiations
u_saltrxdeser	SaltRxDeser <Entity SaltRxDeser>
u_gearbox	AsyncGearbox <Entity AsyncGearbox>
u_decoder	Decoder8b10b <Entity Decoder8b10b>
u_gearboxaligner	SelectIoRxGearboxAligner <Entity SelectIoRxGearboxAligner>
u_syncconfig	SynchronizerVector <Entity SynchronizerVector>

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The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltRxLvds.vhd