SaltRxDeser Entity Reference

Inheritance diagram for SaltRxDeser:

Collaboration diagram for SaltRxDeser:

Entities
SaltRxDeser.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SIM_DEVICE_G	string := " ULTRASCALE "
IODELAY_GROUP_G	string := " SALT_GROUP "
REF_FREQ_G	real := 200 . 0

Ports
rxP	in	sl
rxN	in	sl
clkx4	in	sl
clkx1	in	sl
rstx1	in	sl
dlyLoad	in	sl
dlyCfg	in	slv ( 8 downto 0 )
dataOut	out	slv ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• protocols/salt/rtl/7Series/SaltRxDeser.vhd
• protocols/salt/rtl/UltraScale/SaltRxDeser.vhd