SaltRxLvds Entity Reference

Inheritance diagram for SaltRxLvds:

Collaboration diagram for SaltRxLvds:

Entities
SaltRxLvds.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
Code8b10bPkg	Package <Code8b10bPkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
SIM_DEVICE_G	string := " ULTRASCALE "
IODELAY_GROUP_G	string := " SALT_GROUP "
REF_FREQ_G	real := 200 . 0

Ports
clk125MHz	in	sl
rst125MHz	in	sl
clk156MHz	in	sl
rst156MHz	in	sl
clk625MHz	in	sl
rxEn	out	sl
rxErr	out	sl
rxData	out	slv ( 7 downto 0 )
rxLinkUp	out	sl
enUsrDlyCfg	in	sl := ' 0 '
usrDlyCfg	in	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
bypFirstBerDet	in	sl := ' 1 '
minEyeWidth	in	slv ( 7 downto 0 ) := toSlv ( 80 , 8 )
lockingCntCfg	in	slv ( 23 downto 0 ) := ite ( SIMULATION_G , x " 00_0064 " , x " 00_FFFF " )
rxP	in	sl
rxN	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltRxLvds.vhd