ClinkDataShift.structure Architecture Reference

Architecture >> ClinkDataShift::structure

Signals
intClk	sl
intRst	sl
intClk7x	sl
intClk7xInv	sl
intDelay	slv ( 4 downto 0 )
intLd	sl
cblInDly	slv ( 4 downto 0 )
cblIn	slv ( 4 downto 0 )
rawIn	slv ( 4 downto 0 )
dataShift	Slv7Array ( 4 downto 0 )
clkReset	sl
intClk4x	sl
intClk1x	sl
intDelay	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
serdes	Slv8Array ( 4 downto 0 )
dlyRstL	sl

Attributes
IODELAY_GROUP	string
IODELAY_GROUP	label is " CLINK_CORE "

Instantiations
u_clkinfreq	SyncClockFreq <Entity SyncClockFreq>
u_clinkclkfreq	SyncClockFreq <Entity SyncClockFreq>
u_clkgen	ClinkDataClk <Entity ClinkDataClk>
u_syncdelay	SynchronizerFifo <Entity SynchronizerFifo>
u_inbuff	iobufds
u_delay	idelaye2
u_serdes	iserdese2
u_clkinfreq	SyncClockFreq <Entity SyncClockFreq>
u_clinkclkfreq	SyncClockFreq <Entity SyncClockFreq>
u_mmcm	ClockManagerUltraScale <Entity ClockManagerUltraScale>
u_syncdelay	SynchronizerFifo <Entity SynchronizerFifo>
u_inbuff	iobufds
u_delay	Idelaye3Wrapper <Entity Idelaye3Wrapper>
u_serdes	iserdese3
u_gearbox	AsyncGearbox <Entity AsyncGearbox>

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The documentation for this design unit was generated from the following files:

• protocols/clink/7Series/ClinkDataShift.vhd
• protocols/clink/UltraScale/ClinkDataShift.vhd