SyncClockFreq Entity Reference

Inheritance diagram for SyncClockFreq:

Collaboration diagram for SyncClockFreq:

Entities
SyncClockFreq.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
USE_DSP_G	string := " no "
REF_CLK_FREQ_G	real := 200 . 0E + 6
REFRESH_RATE_G	real := 1 . 0E + 3
CLK_LOWER_LIMIT_G	real := 159 . 0E + 6
CLK_UPPER_LIMIT_G	real := 161 . 0E + 6
COMMON_CLK_G	boolean := false
CNT_WIDTH_G	positive := 32

Ports
freqOut	out	slv ( CNT_WIDTH_G- 1 downto 0 )
freqUpdated	out	sl
locked	out	sl
tooFast	out	sl
tooSlow	out	sl
clkIn	in	sl
locClk	in	sl
refClk	in	sl

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncClockFreq.vhd
• build/SRC_VHDL/surf/SyncClockFreq.vhd