SyncClockFreq.rtl Architecture Reference

Architecture >> SyncClockFreq::rtl

Processes
PROCESS_65	( clkIn )
PROCESS_66	( refClk )
PROCESS_67	( locClk )
PROCESS_174	( clkIn )
PROCESS_175	( refClk )
PROCESS_176	( locClk )

Constants
REFRESH_MAX_CNT_C	natural := getTimeRatio ( REF_CLK_FREQ_G , REFRESH_RATE_G )
CLK_LOWER_LIMIT_C	natural := getTimeRatio ( CLK_LOWER_LIMIT_G , 1 . 0E + 0 )
CLK_UPPER_LIMIT_C	natural := getTimeRatio ( CLK_UPPER_LIMIT_G , 1 . 0E + 0 )

Signals
updated	sl
lockedDet	sl
tooFastDet	sl
tooSlowDet	sl
wrEn	sl
doneAccum	sl
freqHertz	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntIn	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntOut	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntStable	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntAccum	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
accum	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntOutDly	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
diffCnt	slv ( CNT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
use_dsp	string
use_dsp	signal is USE_DSP_G

Instantiations
synchronizerfifo_in	SynchronizerFifo <Entity SynchronizerFifo>
u_sync	SynchronizerFifo <Entity SynchronizerFifo>
synchronizerfifo_in	SynchronizerFifo <Entity SynchronizerFifo>
u_sync	SynchronizerFifo <Entity SynchronizerFifo>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncClockFreq.vhd
• build/SRC_VHDL/surf/SyncClockFreq.vhd