Idelaye3Wrapper Entity Reference

Inheritance diagram for Idelaye3Wrapper:

Collaboration diagram for Idelaye3Wrapper:

Entities
Idelaye3Wrapper.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
CASCADE	string := " NONE "
DELAY_FORMAT	string := " TIME "
DELAY_SRC	string := " IDATAIN "
DELAY_TYPE	string := " FIXED "
DELAY_VALUE	integer := 0
IS_CLK_INVERTED	bit := ' 0 '
IS_RST_INVERTED	bit := ' 0 '
REFCLK_FREQUENCY	real := 300 . 0
SIM_DEVICE	string := " ULTRASCALE "
UPDATE_MODE	string := " ASYNC "

Ports
BUSY	out	sl
CASC_OUT	out	sl
CNTVALUEOUT	out	slv ( 8 downto 0 )
DATAOUT	out	sl
CASC_IN	in	sl
CASC_RETURN	in	sl
CE	in	sl
CLK	in	sl
CNTVALUEIN	in	slv ( 8 downto 0 )
DATAIN	in	sl
EN_VTC	in	sl
IDATAIN	in	sl
INC	in	sl
LOAD	in	sl
RST	in	sl

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The documentation for this design unit was generated from the following files:

• xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd
• xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd