Architecture >> AxiStreamPacketizer2Tb::tb

Constants
TPD_G	time := 1 ns
CRC_EN_G	boolean := false
CRC_POLY_G	slv ( 31 downto 0 ) := x " 04C11DB7 "
MAX_PACKET_BYTES_G	*integer := 256 8**
OUTPUT_SSI_G	boolean := true
INPUT_PIPE_STAGES_G	integer := 0
OUTPUT_PIPE_STAGES_G	integer := 0
NUM_CHANNELS_C	integer := 4
PACKETIZER_IN_AXIS_CFG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )

Signals
axisClk	sl
axisRst	sl
rearbitrate	sl
prbsTxAxisMasters	AxiStreamMasterArray ( NUM_CHANNELS_C- 1 downto 0 )
prbsTxAxisSlaves	AxiStreamSlaveArray ( NUM_CHANNELS_C- 1 downto 0 )
muxAxisMaster	AxiStreamMasterType
muxAxisSlave	AxiStreamSlaveType
packetizedAxisMaster	AxiStreamMasterType
packetizedAxisSlave	AxiStreamSlaveType
depacketizedAxisMaster	AxiStreamMasterType
depacketizedAxisSlave	AxiStreamSlaveType
demuxedAxisMasters	AxiStreamMasterArray ( NUM_CHANNELS_C- 1 downto 0 )

Instantiations
u_clkrst_1	ClkRst <Entity ClkRst>
u_ssiprbstx_1	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreammux_1	AxiStreamMux <Entity AxiStreamMux>
u_axistreampacketizer2	AxiStreamPacketizer2 <Entity AxiStreamPacketizer2>
u_axistreamdepacketizer2_1	AxiStreamDepacketizer2 <Entity AxiStreamDepacketizer2>
u_axistreamdemux_1	AxiStreamDeMux <Entity AxiStreamDeMux>
u_clkrst_1	ClkRst <Entity ClkRst>
u_ssiprbstx_1	SsiPrbsTx <Entity SsiPrbsTx>
u_axistreammux_1	AxiStreamMux <Entity AxiStreamMux>
u_axistreampacketizer2	AxiStreamPacketizer2 <Entity AxiStreamPacketizer2>
u_axistreamdepacketizer2_1	AxiStreamDepacketizer2 <Entity AxiStreamDepacketizer2>
u_axistreamdemux_1	AxiStreamDeMux <Entity AxiStreamDeMux>

The documentation for this design unit was generated from the following files:

Constants

Signals