AxiStreamPacketizer2 Entity Reference

Inheritance diagram for AxiStreamPacketizer2:

Collaboration diagram for AxiStreamPacketizer2:

Entities
AxiStreamPacketizer2.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiStreamPacketizer2Pkg	Package <AxiStreamPacketizer2Pkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
MEMORY_TYPE_G	string := " distributed "
REG_EN_G	boolean := false
CRC_MODE_G	string := " DATA "
CRC_POLY_G	slv ( 31 downto 0 ) := x " 04C11DB7 "
MAX_PACKET_BYTES_G	positive := 256 * 8
SEQ_CNT_SIZE_G	positive range 4 to 16 := 16
TDEST_BITS_G	natural := 8
OUTPUT_TDEST_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
OUTPUT_TID_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
rearbitrate	out	sl
maxPktBytes	in	slv ( bitSize ( MAX_PACKET_BYTES_G ) - 1 downto 0 ) := toSlv ( MAX_PACKET_BYTES_G , bitSize ( MAX_PACKET_BYTES_G ) )
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamPacketizer2.vhd
• protocols/packetizer/rtl/AxiStreamPacketizer2.vhd