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AxiStreamPacketizer2.rtl Architecture Reference
Architecture >> AxiStreamPacketizer2::rtl

Processes

comb  ( crcOut , crcRem , inputAxisMaster , maxWords , outputAxisSlave , r , ramCrcRem , ramPacketActiveOut , ramPacketSeqOut )
seq  ( axisClk , axisRst )
comb  ( crcOut , crcRem , inputAxisMaster , maxWords , outputAxisSlave , r , ramCrcRem , ramPacketActiveOut , ramPacketSeqOut )
seq  ( axisClk , axisRst )

Constants

AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
LD_WORD_SIZE_C  positive := 3
WORD_SIZE_C  positive := 2 ** LD_WORD_SIZE_C
PROTO_WORDS_C  positive := 3
MAX_WORD_COUNT_C  WordCounterType := to_unsigned ( MAX_PACKET_BYTES_G/ WORD_SIZE_C , WordCounterType ' length )
CRC_EN_C  boolean := ( CRC_MODE_G/ = " NONE " )
CRC_HEAD_TAIL_C  boolean := ( CRC_MODE_G = " FULL " )
ADDR_WIDTH_C  positive := ite ( ( TDEST_BITS_G = 0 ) , 1 , TDEST_BITS_G )
RAM_DATA_WIDTH_C  positive := 32 + 1 + SEQ_CNT_SIZE_G
REG_INIT_C  RegType := ( state = > HEADER_S , packetSeq = > ( others = > ' 0 ' ) , packetActive = > ' 0 ' , activeTDest = > ( others = > ' 0 ' ) , ramWe = > ' 0 ' , wordCount = > ( others = > ' 0 ' ) , maxWords = > to_unsigned ( 1 , WordCounterType ' length ) , eof = > ' 0 ' , lastByteCount = > " 1000 " , tUserLast = > ( others = > ' 0 ' ) , rearbitrate = > ' 0 ' , crcDataValid = > ' 0 ' , crcDataWidth = > ( others = > ' 1 ' ) , crcInit = > ( others = > ' 1 ' ) , crcRem = > ( others = > ' 1 ' ) , crcIn = > ( others = > ' 1 ' ) , crcReset = > ' 0 ' , tailCrcReady = > toSl ( not CRC_HEAD_TAIL_C ) , inputAxisSlave = > AXI_STREAM_SLAVE_INIT_C , outputAxisMaster = > axiStreamMasterInit ( PACKETIZER2_AXIS_CFG_C ) )

Types

StateType  ( IDLE_S , WAIT_S , HEADER_S , MOVE_S , TAIL_S )

Subtypes

WordCounterType  unsigned ( maxPktBytes ' left- LD_WORD_SIZE_C downto 0 )

Signals

r  RegType := REG_INIT_C
rin  RegType
inputAxisMaster  AxiStreamMasterType
inputAxisSlave  AxiStreamSlaveType
outputAxisMaster  AxiStreamMasterType
outputAxisSlave  AxiStreamSlaveType
ramDin  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
ramDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
ramPacketSeqOut  slv ( SEQ_CNT_SIZE_G- 1 downto 0 )
ramPacketActiveOut  sl
ramCrcRem  slv ( 31 downto 0 ) := ( others = > ' 1 ' )
ramAddrr  slv ( ADDR_WIDTH_C- 1 downto 0 )
crcIn  slv ( 63 downto 0 ) := ( others = > ' 1 ' )
crcOut  slv ( 31 downto 0 ) := ( others = > ' 0 ' )
crcRem  slv ( 31 downto 0 ) := ( others = > ' 1 ' )
maxWords  WordCounterType

Records

RegType 

Instantiations

u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_dualportram_1  DualPortRam <Entity DualPortRam>
u_crc32  Crc32Parallel <Entity Crc32Parallel>
u_crc32  Crc32 <Entity Crc32>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>
u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_dualportram_1  DualPortRam <Entity DualPortRam>
u_crc32  Crc32Parallel <Entity Crc32Parallel>
u_crc32  Crc32 <Entity Crc32>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>
The documentation for this design unit was generated from the following files: