Crc32 Entity Reference

Inheritance diagram for Crc32:

Entities
Crc32.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
CrcPkg	Package <CrcPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
BYTE_WIDTH_G	positive := 4
INPUT_REGISTER_G	boolean := true
CRC_INIT_G	slv ( 31 downto 0 ) := x " FFFFFFFF "
CRC_POLY_G	slv ( 31 downto 0 ) := x " 04C11DB7 "

Ports
crcPwrOnRst	in	sl := not RST_POLARITY_G
crcOut	out	slv ( 31 downto 0 )
crcRem	out	slv ( 31 downto 0 )
crcClk	in	sl
crcDataValid	in	sl
crcDataWidth	in	slv ( 2 downto 0 )
crcIn	in	slv ( ( BYTE_WIDTH_G* 8 - 1 ) downto 0 )
crcInit	in	slv ( 31 downto 0 ) := CRC_INIT_G
crcReset	in	sl

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The documentation for this design unit was generated from the following files:

• base/crc/rtl/Crc32.vhd
• build/SRC_VHDL/surf/Crc32.vhd