AxiStreamDepacketizer2 Entity Reference

Inheritance diagram for AxiStreamDepacketizer2:

Collaboration diagram for AxiStreamDepacketizer2:

Entities
AxiStreamDepacketizer2.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiStreamPacketizer2Pkg	Package <AxiStreamPacketizer2Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
MEMORY_TYPE_G	string := " distributed "
REG_EN_G	boolean := false
CRC_PIPELINE_G	natural range 0 to 1 := 0
CRC_MODE_G	string := " DATA "
CRC_POLY_G	slv ( 31 downto 0 ) := x " 04C11DB7 "
SEQ_CNT_SIZE_G	natural range 0 to 16 := 16
TDEST_BITS_G	natural := 8
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 1

Ports
axisClk	in	sl
axisRst	in	sl
linkGood	in	sl
debug	out	Packetizer2DebugType
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamDepacketizer2.vhd
• protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd